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From:	RayeR <glaux AT centrum DOT cz>
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: jitter between 2 hardware interrupt
Date:	Sat, 6 Mar 2010 07:13:42 -0800 (PST)
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I suspect that this behavior have something to do with PC SMBIOS/SMI.
This is heavily used in modern PC for power management, error
signalling and even emulating legacy hardware.

CPU can be set in real mode, protected mode and SMM (System Management
Mode) mode.
SMM mode is entered when SMI (System Management Interrupt) is
triggered.
CPU has separated SMI pin that is fed from chipset. It has higher
priority than NMI and I think it
cannot be disabled for safety reasons. When SMI occured CPU switch to
SMI handler.
This is done in real mode as well as in protected mode. Entire CPU
context is saved.
SMI handler determine the cause of SMI and call the matching service.
It can take some time of course.
Finally it restore CPU context and switch back to RM/PM. So running
operating system cannot recognize
this interrupt. I think this approach is also used for USB storages
emulating real drives. SMI
BIOS cannot be completly disabled but by disabling some legacy support
or power management stuff
you may save some time... If you run your program on some old 486 or
Pentium 1 you should
notice much less jitter caused by this.

Next I give you warning when using RDTSC. On mobile systems there are
various power saving features
like intel speedstep or EIST that cause CPU clock mudulation or
dynamic core multiplier change which
cause that you cannot rely on TSC that it runs on constant speed! I
had some bad story with this when
trying to use TSC for some short time measurement.

On 4 b=C5=99e, 20:07, "Josep M." <josepma DOT  DOT  DOT  AT turomas DOT com> wrote:
> I don't know why, but there are som bios task wich interrupts processor a=
nd
> I can not disable too.

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