Mail Archives: djgpp/2009/05/04/23:11:41
> From: Rugxulo <rugxulo AT gmail DOT com>
> Date: Mon, 4 May 2009 15:07:21 -0700 (PDT)
>
> > As Charles points out, adding
> > SSE support will need code added to determine whether FXSAVE/FXRSTOR
> > are supported before we use them, and a lot of testing to make sure we
> > don't break old machines.
>
> 1). See if CPUID supported (bit 21 of eflags)
> 2). See if FXSAVE / FXRSTOR supported (bit 24 of edx result from cpuid
> eax=1)
> 3). See if SSE supported (SSE1 is bit 25 of edx result from cpuid
> eax=1, SSE2 is bit 26, SSE3 is bit 0 of ecx)
> 4). If not already using CWSDPMI r5 2008, set bit 9 (OSFXSR) of CR4
> and turn off bit 2 of CR0 (EM - emulation) -- typically done in ring
> 0, but some ring 3 environments emulate it for you (JEMM386)
Yes, and then test a lot on old machines which I don't even know where
to find. All this just to have a change in a version that isn't going
to be released any time soon? Doesn't sound like a good investment of
my scarce resources.
> > OTOH, if someone needs it badly on a machine that is known to support
> > these instructions, they can simply replace FNSAVE/FRSTOR with the
> > extended instructions, modify the definition of the NPX object in
> > debug/dbgcom.h to accommodate for the extra registers, and be done.
>
> You make it sound trivial, not sure it is.
It's trivial. You can try it.
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