Mail Archives: djgpp/2004/07/23/21:15:51
Matt Flyer <goaway AT nospam DOT me> wrote:
1. I'd appreciate it if you DIDN'T top post.
2. I'd appriciate it if you cut out the irrelevent parts of what
you're replying to. This might be a side-affect from 1.
: That would seem to make sense. I also noticed that what ever routine is
: getting called in the chain is masking out the irq10 ?HUH?? so I have had
: better results claiming the interrupt myself.
When an interrupt occurs it is masked until "claimed" (I don't
remember the terminlogy; until the interrupt controller is reset, I
mean.)
: The picture actually gets more murkey. It turns out that I now have the
: interrupt occuring multiple times. For some reason it only happens about
: 10 - 12 times though then stops. The pic controllers indicate that the
: interrupts are enabled and sometimes I get that they're in service.
: At the moment, I think my suspicion that there is some difference in the way
: the compiled code that handles the interrupt as I get different results. I
: haven't been able to work on it much recently though as I have been putting
: out other "fires" at work.
As I said I haven't done any hardware catching myself, but you are
aware of that the IRQ might be redirected to some other INT base,
aren't you? (CWSDPMI does reprogram the PIC.)
Are you sure you aren't getting more interrupts than you can handle
(timewise)?
Right,
MartinS
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