From:	"Ben Peddell" <killer DOT lightspeed AT bigpond DOT com>
Newsgroups:	comp.os.msdos.djgpp
References:	<12212N341 AT web2news DOT com> <GN9X9.29467$jM5 DOT 76104 AT newsfeeds DOT bigpond DOT com> <12335N735 AT web2news DOT com>
Subject:	Re: C/C++ versions of asm opcodes.
Lines:	36
X-Priority:	3
X-MSMail-Priority:	Normal
X-Newsreader:	Microsoft Outlook Express 5.00.2615.200
X-MimeOLE:	Produced By Microsoft MimeOLE V5.00.2615.200
Message-ID:	<o3vX9.30300$jM5.78313@newsfeeds.bigpond.com>
Date:	Wed, 22 Jan 2003 20:16:53 +1000
NNTP-Posting-Host:	144.139.175.5
X-Trace:	newsfeeds.bigpond.com 1043234132 144.139.175.5 (Wed, 22 Jan 2003 22:15:32 EST)
NNTP-Posting-Date:	Wed, 22 Jan 2003 22:15:32 EST
Organization:	Telstra BigPond Internet Services (http://www.bigpond.com)
To:	djgpp AT delorie DOT com
DJ-Gateway:	from newsgroup comp.os.msdos.djgpp
Reply-To:	djgpp AT delorie DOT com

There are also RCL and RCR, which would need the Rotate and Shift operations
I gave to also have a carry flag. RCL and RCR are useful when you want to
rotate values of more than 32 bits by 1 bit at a time. Otherwise, I don't
know why Intel allowed RCL and RCR to have shift amounts of more than 1 bit.
Maybe they just wanted to give RCL/RCR equal footing to the other
shift/rotate operations.

unsigned long rcl (unsigned long src, unsigned long samt, int *carry){
    unsigned long dst;
    samt &= 31;
    if (samt == 0){
        dst = src;
    } else {
        dst = (src << samt) | (src >> (33 - samt)) | (carry ? (1 << (samt -
1)) : 0);
        carry = src & (1 << (32 - samt));
    }
    return dst;
}

unsigned long rcr (unsigned long src, unsigned long samt, int *carry){
    unsigned long dst;
    samt &= 31;
    if (samt == 0){
        dst = src;
    } else {
        dst = (src >> samt) | (src << (33 - samt)) | (carry ? (1 << (32 -
samt)) : 0);
        carry = src & (1 << (samt - 1));
    }
    return dst;
}

- Raw text -