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Date:	Sun, 13 Jan 2002 18:43:13 +0200
From:	"Eli Zaretskii" <eliz AT is DOT elta DOT co DOT il>
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To:	Martin Steuer <martinSteuer AT gmx DOT de>
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In-reply-to:	<5.0.2.1.2.20020113120630.009e6c70@pop.gmx.net> (message from
	Martin Steuer on Sun, 13 Jan 2002 12:27:49 +0100)
Subject:	Re: Setting Env Var from within make
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> Date: Sun, 13 Jan 2002 12:27:49 +0100
> From: Martin Steuer <martinSteuer AT gmx DOT de>
> 
> So now when i include the *.d dependecies the targets names are not the 
> same and so make won't check for the change of the include files it just 
> uses the above rule.
> So every time gcc is invoked i want to change the content of 
> DEPENDENCIES_OUTPUT where you can directly specify the targets name as the 
> second value (i'd use $@ for it).
> 
> It could be so easy if i could specify the targets name directly to gcc, 
> i'm currently using version 2.952, i think thats a feature which should be 
> added to later versions (maybe it has already been done?).

In GCC 3.0.2, you have "-MF FILE", which I think will do what you
want.  I don't know in what version was -MF introduced.

> I really want to do it this way because i think the whole directory 
> structure is much clearer.

I can think about two options:

  - Run GCC as usual with -MMD, then move the .d file to the
    directory where you want it (I assume that all the .d files
    should end up in the same directory).

  - Invoke Make recursively.  Here's an example (untested):

OBJPATH = ./obj/

$(target): $(source)
	 $(CC) $(CFLAGS) -c $< -o $(OBJPATH)$*.o

$(OBJPATH)%.o : %.c
	$(MAKE) $(MAKEFLAGS) $@ target=$@ source=$< DEPENDENCIES_OUTPUT=$*.d

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