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From: | "Campbell, Rolf [SKY:1U32:EXCH]" <moscoop AT americasm01 DOT nt DOT com> |
Newsgroups: | comp.os.msdos.djgpp |
Subject: | Re: AMD processors and assembly language |
Date: | Tue, 14 Mar 2000 16:03:39 -0500 |
Organization: | Nortel Networks |
Lines: | 20 |
Message-ID: | <38CEA92B.33F326B@americasm01.nt.com> |
References: | <slrn8cl4ci DOT sv DOT wilmer AT syscon DOT minilinux DOT org> <Pine DOT LNX DOT 4 DOT 10 DOT 10003120901480 DOT 1343-100000 AT darkstar DOT grendel DOT net> <0damcssmqrmoiphi95hu789fkkfhpgk327 AT 4ax DOT com> |
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To: | djgpp AT delorie DOT com |
DJ-Gateway: | from newsgroup comp.os.msdos.djgpp |
Reply-To: | djgpp AT delorie DOT com |
Damian Yerrick wrote: > >Yes, most likely, but what I wanted to point out is the awesome > >overcloackbility of the athlons ... > > Speaking of Athlon: > Athlon is a VLIW RISC chip with a hardware Intel emulator frontend. And, ironically, the 'emulation' runs faster than the original (at the same clock speed). > Crusoe is a VLIW RISC chip with a software Intel emulator frontend > called "Code Morphing(tm)". IA64 Merced Itanium (or whatever it's > called) is a VLIW RISC chip with a totally new instruction set. -- (\/) Rolf Campbell (\/)
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