Sender:	root AT delorie DOT com
Message-ID:	<38C7FBBD.3D921E9C@inti.gov.ar>
Date:	Thu, 09 Mar 2000 16:30:05 -0300
From:	salvador <salvador AT inti DOT gov DOT ar>
Organization:	INTI
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To:	djgpp AT delorie DOT com, Dieter Buerssner <buers AT gmx DOT de>
Subject:	Re: [long] gcc performance and possible bug
References:	<Pine DOT SUN DOT 3 DOT 91 DOT 1000307103019 DOT 21628J-100000 AT is> <8a65uu$39fkt$1 AT fu-berlin DOT de> <38C6B414 DOT 2D67E404 AT inti DOT gov DOT ar> <8a70n9$34mhh$1 AT fu-berlin DOT de>
Reply-To:	djgpp AT delorie DOT com

Dieter Buerssner wrote:

> salvador) wrote:
>
> >K6 CPUs have a "bug" related to aligment. If some memory address is in a
> >0xNNNNNC, you'll have a big penalty to read it. 0, 4 and 8 are ok,
> >but C is the worst case (by far), double check you are not hiting this
> >limitation.
>
> Do you mean code alignment, data alignment or both?

I saw it in code, but I think data could be affected equally.

> Anyway, I edited the gcc -O2 -S output of the slower running version
> of my program (with const), changed the .p2align 2 statements to
> .p2align 4 (16 byte), for zseed, mul and mwc32 (I think these
> are all data and code alignments that could contribute to the
> large performance difference), and recompiled. The program
> was ran faster, but there was still an order of magnitude difference
> between the const and the non const version.
>
> I also double checked the alignments with fsdb and objdump (Thanks to
> Hans-Bernhard Broeker, for pointing the objdump method out to me).
> zseed, mul and mwc32 were 16 byte aligned.
>
> If you have the time and the interest, please try to compile the
> source I sent and run the executable. It should take less than five
> minutes.

Send me a copy, I don't have it here.

SET

--
Salvador Eduardo Tropea (SET). (Electronics Engineer)
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