Mail Archives: djgpp/1998/07/03/11:08:28
"Arthur" <arfa AT clara DOT net> wrote:
> >Sorry, you're wrong. The Intel 80x86 machines are 2's complement.
> >This means that -2 is 11111110. Shifted left this produces 11111100, or
> >-4.
> >SHL and SAL are the same bytecode on Intel 80x86.
> >CF <- register <- 0 (high bit is shifted into the CF (carry flag),
> >zero is shifted into the least significant bit)
> >
> >SHR and SAR are different bytecodes however.
> >SHR produces
> >0 -> register -> CF (0 is shifted into high bit, low bit is shifted
> >into CF (carry flag))
> >whereas SAR produces
> >sign bit -> register -> CF (the sign bit is replicated in the high
> >bit, low bit is shifted into CF (carry flag))
>
>
> Oh, for a decent processor. I'm sorely tempted to go back to my ST.
>
> >> These are obviously different to arethmetic shifts.
> >Only on the Motorola (and similar) chips. Not on the Intel 80x86.
>
>
> You say "only." I know of no other processor other than the x86 (and
> compatibles) that have such an illogical and unfriendly instruction set.
That's because you don't know much about RISC processors.
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