Mail Archives: djgpp/1997/03/22/07:44:19
From: | "Colin W. Glenn" <cwg01 AT gnofn DOT org>
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Newsgroups: | comp.os.msdos.djgpp
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Subject: | Re: DJGPP gurus: interrupts wrappers are reentrant ?
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Date: | Fri, 21 Mar 1997 21:34:53 -0600
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Organization: | Greater New Orleans Free-Net
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Lines: | 22
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Message-ID: | <Pine.GSO.3.95.970321213302.23040I-100000@sparkie.gnofn.org>
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References: | <332BADAD DOT 63C7A87E AT lmn DOT pub DOT ro> <01bc34b3$b02471a0$LocalHost AT anthonyb>
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NNTP-Posting-Host: | sparkie.gnofn.org
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Mime-Version: | 1.0
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In-Reply-To: | <01bc34b3$b02471a0$LocalHost@anthonyb>
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To: | djgpp AT delorie DOT com
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DJ-Gateway: | from newsgroup comp.os.msdos.djgpp
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Pardon me for sticking my two cents in here, but wasn't the prior state of
the interrupt flag pushed on the stack with the rest? And doesn't a IRET
pop the flags and restore that state?
On 20 Mar 1997, Anthony Q. Bachler wrote:
> Try clearing the interupt enable bit of the MSW as one of the first steps
> in the ISR. This will cause the hardware to store any interupts that occur
> and execute them when you reenable them. To disable them use the CLI
> assembly instruction. To reenable them use the STI instruction. A word of
> caution, STI should be immediately followed by an IRET to prevent the
> problem you are experienceing. The problem you are having is that the
> stack is being corrupted. When you perform an STI, the processor should
> hold off executing any pending interupts until after the next command. I
> know for a fact that it works this way on the 8086-80686. On a different
> processor, it may work differently. The above details are for the intel
> CPU's, but the method is the same for most others.
--
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