Mail Archives: djgpp/1996/12/01/13:03:58
In article <32b1ba0f DOT 58325187 AT news DOT pacificnet DOT net>, Kevin AT Quitt DOT net wrote:
>The P6 instruction cache, for example, is sensitive to the instructions
>therein and will prefetch from both possible targets of a conditional
>jump (before the instruction even gets to the processor). That's why
>absolute and conditional jumps are now considered to take zero
>cycles on advanced processors like the P6 and 68060.
I know this is off-topic, but I can't help it. Anyone know if the
P6 implements branch folding? I didn't think it did, but from the
sounds of your post, it does.
Jimmy Wan University of Michigan-Computer Engineering
Turtle Beach Maui Page http://www-personal.umich.edu/~vecna/maui.html
Device Driver Page http://www-personal.umich.edu/~vecna/drivers.html
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