Xref:	news2.mv.net comp.os.msdos.djgpp:4284
From:	wildfire AT artifax DOT com (Rain Ouellet)
Newsgroups:	comp.os.msdos.djgpp
Subject:	More Make Woes
Date:	Mon, 27 May 1996 08:29:17 GMT
Organization:	Wildfire Design Studios
Lines:	39
Distribution:	world
Message-ID:	<4obpig$obj@atlas.uniserve.com>
Reply-To:	wildfire AT artifax DOT com
NNTP-Posting-Host:	van0228.tvs.net
To:	djgpp AT delorie DOT com
DJ-Gateway:	from newsgroup comp.os.msdos.djgpp

Perhaps someone can figure this one out.  I've been using makefiles
for ages with setups similar to the following:

CC = MyCompiler

..c.obj:
   $(CC) -c $<

..obj.exe:
   $(CC) $<

all: file1.exe file2.exe file3.exe

file1.exe: file1.obj
file2.exe: file2.obj
file3.exe: file3.obj

file1.obj: file1.c  
file2.obj: file2.c  
file3.obj: file3.c  

 Indeed, I just ran almost exactly this (filenames obviously changed)
under three different make utilities, and they all happily ate it.
Except, of course, for GNU make.  It insists:

"makefile:7: *** missing separator.   Stop."

  In this case, the offending line is the first instance of:
 
      $(CC) -c $<
 
 Okay, great.  What separator is missing?  Maybe I'm missing something
obvious, but I'll be hanged if I can figure out, even from the
so-called "documentation", what's going wrong.

  Any help would be much appreciated.

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