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From: | Charles Sandmann <sandmann AT clio DOT rice DOT edu> |
Newsgroups: | comp.os.msdos.djgpp |
Subject: | Re: locking for HW ints/RMCB |
Date: | Mon, 18 Sep 1995 21:05:11 CDT |
Organization: | Rice University, Houston, Texas |
Lines: | 14 |
References: | <434fn5$bgm AT newsie DOT wis DOT com> <43bf3v$6rm AT mrnews DOT mro DOT dec DOT com> <43b559$e6 AT alijku06 DOT edvz DOT uni-linz DOT ac DOT at> <43i3j7$fnq AT st-james DOT comp DOT vuw DOT ac DOT nz> |
Reply-To: | sandmann AT clio DOT rice DOT edu |
Nntp-Posting-Host: | clio.rice.edu |
To: | djgpp AT sun DOT soe DOT clarkson DOT edu |
Dj-Gateway: | from newsgroup comp.os.msdos.djgpp |
> How can you make sure that the stack in an assembly HW int handler is > locked. You can keep the code and data within boundaries, but the stack > is accessed before you get to change the stack registers (ie to save > CS:EIP), or does this one use of the stack not matter (page almost always > will be in memory as the program itself is using it)? All Hardware interrupts and RMCBs are handled on a locked 4Kb stack provided by the DPMI provider (so SS:ESP won't be in the DJGPP address space). The _go32_dpmi ... wrappers swap onto a local 64K stack in the DJGPP address space so SS=DS and GCC's code won't get confused (then jump back on exit). So, if you write in assembler, you know that DS != SS and can handle this, also knowing you must minimize stack use (with only 4K available for all nested interrupts/execeptions).
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