Mail Archives: djgpp/1994/05/23/11:44:17
> Guarionex Morales wrote:
> > The memory mapped devices introduce yet another problem that I
> > have'nt seen mentioned in the list yet. For data integrity,
> > caching has to be disabled for the memory area where the device is
> > mapped onto.
>
> There is a good reason you didn't see this on the list: the problem does
> not exist. Motherboard manufacturers did already take (hopefully good) care
> of this by DISABLING the cache automagically when reading from the address
> range where memory-mapped devices usually sit (on a PC, this would be A000 -
> FFFF). It must be this way, because otherwise no memory-mapped device would
> work, as programs usually don't distinguish between memory located on the
> motherboard vs on a periferal card.
CMOS setup programs sometimes let you select which memory areas in the
A000-FFFF range are cacheable or shadowable, and these setting may be
critical in determining whether a peripheral will work. The more interesting
case is a device with memory beyond the first MB. I don't really know how
these work with a cache, but as you say, they must have a way of invalidating
the cache or they wouldn't work at all.
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