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From:	Brian Inglis <Brian DOT Inglis AT SystematicSW DOT ab DOT ca>
To:	cygwin AT cygwin DOT com
Date:	Sun, 07 Nov 2021 00:03:58 -0600
Message-Id:	<announce.20211107000358.50902-1-Brian.Inglis@SystematicSW.ab.ca>
Subject:	[ANNOUNCEMENT] Updated: cpuid 20211031
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The following package has been updated in the Cygwin distribution:

* cpuid 20211031

The program displays detailed information about the CPU(s) gathered from
the CPUID instruction, and also determines the exact model of CPU(s).

Whereas /proc/cpuinfo is like an abstract of the features important to
Linux in a system, cpuid is a standalone utility which writes a paper
expounding on every feature in each CPU's architecture and what it can
do, at about the one line per bit level.

It is updated and released frequently and appears current with Intel and
AMD info and supports other vendors' chips.


See the project home page for more information:

http://etallen.com/cpuid.html


Changes

* Support hypervisors which can move their range of leaves to other base
  addresses, to support hypervisors under other hypervisors
* print hypervisor_id values that contain non-graphic characters.
* Improved (synth) decoding for Intel Xeon (3rd Gen) D2/M1 steppings,
  Tiger Lake: Pentium & Celeron, Elkhart Lake: Pentium & Celeron, Jasper
  Lake: Pentium & Celeron, (0,6)(10,5) Comet Lake: Pentium, Celeron &
  Xeon, (0,6),(6,10) Ice Lake: Xeon Scalable, AMD (8,15),(1,1) Raven
  Ridge: Athlon Pro 200, AMD (8,15),(1,8) Picasso: Athlon Pro 300, Tiger
  Lake, Rocket Lake.
* Added 0x40000001/eax support for ACRN hypervisor.
* Added better decoding of 0x12/1 SECS.ATTRIBUTES fields.
* Added 5,3 model for Cyrix M1 6x86, based on Cyrix 6x86 Processor,
* Instruction Set document (M1-6).
* Corrected wrong register passed to print_40000009_edx_microsoft().
* Improved Cygwin support
* For 12/n/ebx & 12/n/edx (n >= 2), mask the high 12 bits.
* Added 0x40000001/eax(KVM) map gpa range hypercall & MSR_KVM_MIGRATION_CONTROL.
* Add (synth) decoding for additional Alder Lake steppings, Vortex86EX2
  & Vortex86DX2, AMD 4700S Desktop Kit, AMD (8,15),(4,7) Lucienne, AMD
  Milan B1, AMD Vermeer, AMD Cezanne, (6,15),(3,0) AMD R-Series Bald
  Eagle based on instlatx64 sample.
* Generalize (synth) decoding for Elkhart Lake B0.
* Added 0x8000000a/edx guest SVME addr check.
* Added 7/0/ecx bus lock detection.
* Added 7/0/edx RTM transaction always aborts, TSX_FORCE_ABORT.
* Added 0x40000001/eax (KVM) extended destination ID.
* Added 0x80000008/ecx tscSize.
* Added 0x8000001c/{eax,edx} continuous mode sampling.
* Added 0x8000001c/{eax,edx] tsc in event record.
* Renamed 7/0/ecx 5-level paging to include LA57 & 57-bit addrs.
* Improved 0xa/ebx presentation, and automatically mask bits marked as
  invalid by 0xa/eax vector length.
* Added 0x12/n/ecx new section property encoding.
* Renamed Rocket Lake uarch to Cypress Cove.
* Add support for 0x40000003/eax reenlightenment control MSR &
  0x40000003/eax TscInvariant control MSR [on Microsoft Hyper-V].
* restoring the deleted "AMD (unknown model)" entry.
* updates the existing leaf and subleaf in the CPUID with features
  related to INVLPGB, CPPC, PSFD, SEV [affects 0x80000008/edx,
  0x80000008/edx, and 0x8000001f/eax].
* defines new leaf 80000021/eax.
* replaces the naming "Unknown Model" -> "AMD EPYC Milan" for Family 19h
  and Model 01h [affects (synth) decoding].
* From http://datasheets.chipdb.org/Cyrix/112ap.pdf (page 7, table 1):
  Cyrix family 4 model 4 should be MediaGX or GXi; GXm is family 5,
  model 4; Cyrix MediaGX is derived from the 5x86 and unrelated to the
  WinChip C6. Based on Wikipedia, the MediaGXm was renamed the Geode GXm
  after it was sold to National Semi but the CPUs appear to have
  continued to be sold under the Cyrix vendor up to and including the
  Geode GX1. Hence, I've simply duplicated the names from NSC model 4
  into Cyrix.
* Model 9 for the WinChip 3 is moved to the Centaur section
  [decode_synth_via()], from the datasheet page 3-11:
  http://datasheets.chipdb.org/IDT/x86/WinChip3/winchip_3_datasheet.pdf
* The Cyrix CPU detection guide [112ap] also offers some possible
  codenames from page 20, table 17 Cx486SLC/DLC/SRx/DRx (M0.5) up to
  table 26 for the GXm.
* Corrected decode_amd_model()'s (0,15),(4,0) decodings for bti values
  0x29, 0x2a, and 0x2b.
* Corrected wrong register passed to print_40000001_edx_kvm().
* Added rudimentary synth & uarch decoding for Montage Jintide Gen1, a
  CPU based on Intel Skylake (0,6),(5,5), and detectable by brand string.
* Fixed append_uarch() to pass stash, which improves uarch [suffix] for
  Montage, Zhaoxin, and ZhangJiang CPUs.


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