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Date:	Mon, 11 Mar 2019 12:10:53 +0000
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From:	"Kunal Ghosh" <contactvsd AT vlsisystemdesign DOT com>
To:	cygwin AT cygwin DOT com
Require-Recipient-Valid-Since:	cygwin AT cygwin DOT com; Mon, 11 Mar 2019 12:10:16 +0000
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Subject:	Welcome to my community at VLSI SYSTEM DESIGN!!
Sender:	Kunal Ghosh <contactvsd=vlsisystemdesign DOT com AT send DOT aweber DOT com>
X-MIME-Autoconverted:	from quoted-printable to 8bit by delorie.com id x2BCB3xo013289

Hey There,

In case if you plan to visit or any future RISC-V workshop, you should be aware the basics of RISC-V and so here are the downloadable links for all short books on RISC-V which we have published till date. The last book is a strategy on VLSI Physical design implementation of 2 designs using opensource EDA RTL2GDS flow 'qflow'. Download, read and enjoy....


RISC-V Introduction:
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=c8n8ydIW_9FTy4FMjrNx.Q


RISC-V Double-word:
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=30IZwptqm5KgOhf6ONkNCw

Why RISC-V architecture has 32 registers:
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=eGpVUdzFSfh1_E2ldNdV3w

ABI – Get this one right – RISC-V:
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=jWifwo3PvZzAvcZEqcvNfQ–-Get-this-one-right-–-RISC-V.pdf

Wanna quick solution to identify overflows? – Use RISC-V branches
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=hm2GZfhszyjZL24wvUZE4A


From VLSI to System Design (SoC) – The choice of SPI:
https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=4Zok96WglPb8eG.7FudBEg


Book on Physical design using opensource EDA qflow, along with LIVE examples:

https://clicks.aweber.com/y/ct/?l=AZ5mW&m=3yR80EZOX3A8._6&b=Z5yY3fhaOVXP_SXZXLE7dQ



Outer Ring Road
Bangalore
Bangalore Karnataka 560037
INDIA

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