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layout issues

Left: Note that the trace has a clearance approximately the size of the via, and it wipes out part of the thermal. The clearance is causing DRC problems as it's trying to clear copper away from the via as well ('K' on the line clears it completely away from the via).

Right: A better solution is to let the line join with the polygon ('J') and change the via so that the line doesn't interfere with it (Thermal Tool, shift-click).

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