Bitfields for AMD-640 32-bit DRAM Width Control register:
Bit(s) Description )
7 RAS# to Column Address delay (0 = 1T, 1 = 2T)
6 delay NA# by 1T
5-0 widths of banks 5 - 0
AMD-640 documentation clains that all bits should be cleared
for VT82C580VPX, settings are 0 = 64-bit, 1 = 32-bit (only applicable
when two banks of PBSRAM are installed)
SeeAlso: #00983,#00982,#00997,#00999