Bitfields for Intel 82380FB Serial Interface/Burst Enable register:
Bit(s)	Description	)
 15-13	reserved
 12	enable SERR# on discarding of posted write data
 11	reserved
 10	SDATA signal direction (0 = output, 1 = input)
 9	enable write posting
 8	enable read bursting
 7	enable upstream blind prefetching
 6	reserved
 5	SDATA signal state (read when bit 10 set, write when bit 10 clear)
 4	SDIN signal state
 3	do not pulse P_SERR# when S_PERR# is asserted
 2	cascade/frame determination delay (0 = 20 P_CLKs, 1 = 10 P_CLKs)
 1	serial EEPROM chip select
 0	serial EEPROM clock
SeeAlso: #01093