Bitfields for AMD-640 Cache Control Register 1:
Bit(s)	Description	)
 7-6	cache enable
	00 disabled
	01 initialization (BIOS fills L2 cache to known state)
	10 enabled (normal operation)
	11 reserved
 5	reserved (do not change)
 4-3	tag configuration
	00 eight tag bits, no "modify" bit
	01 seven tag bits, one modify bit
	10 ten tag bits, no modify bit
	11 nine tag bits, one modify bit
 2	reserved (0)
 1-0	type of cache RAM
	00 none
	01 reserved
	10 burst SRAM
	11 pipeline burst SRAM
SeeAlso: #00983,#00985