Format of Brooktree Bt8230 ATM controller configuration:
Offset Size Description )
00h 64 BYTEs header (see #00878)
(vendor ID 109Eh, device ID 8230h)
10h DWORD address at which to map external memory (multiple of 16M)
internal registers are mapped at offsets 0000h-01FFh; Bt8222
registers are mapped at 0200h-03FFh, and T1/E1 Framer
registers are mapped at 0800h-0FFFh. Only 32-bit memory
accesses are used
40h BYTE maximum burst length (00h not allowed, default = 10h)
41h BYTE "SPECIAL_STATUS"
bit 3: attempted to perform DMA on PCI while bus-mastering
disabled in PCI command word
bit 2: PCI/DMA synchronization error occurred
bit 1: PCI bus master encountered fatal error
bit 0: direction of transaction which encountered error
=0 write (refer to offset 48h)
=1 read (refer to offset 44h)
Note: bits 3-1 are write-clear, bit 0 is read-only
42h 2 BYTEs unused
44h DWORD current read target address for PCI bus master (read-only)
48h DWORD current write target address for PCI bus master (read-only)
4Ch 180 BYTEs reserved
SeeAlso: #00790