Format of AMD-645 Peripheral Bus Controller, function 3 (Power Mgmt) data:
Offset	Size	Description	)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 1106h, device ID 3040h)
 20h	DWORD	base address for I/O ports (see PORT xxxxh"AMD-645")
 40h	BYTE	pin configuration (see #01050)
 41h	BYTE	general configuration (see #01051)
 42h	BYTE	SCI interrupt configuration (see #01052)
 43h	BYTE	reserved
 44h	WORD	primary interrupt channel
		bit 2 is reserved; setting any other bit N makes IRQN the
		  primary interrupt channel
 46h	WORD	secondary interrupt channel
		bit 2 is reserved; setting any other bit N makes IRQN the
		  secondary interrupt channel
 48h  8 BYTEs	unused???
 50h	DWORD	GP timer control (see #01053)
 54h 13	BYTEs	reserved
 61h	BYTE	programming interface read value (value to be returned by
		  configuration register 09h) (write-only)
 62h	BYTE	subclass read value (value to be returned by
		  configuration register 0Ah) (write-only)
 63h	BYTE	base class read value (value to be returned by configuration
		  register 0Bh) (write-only)
 64h 156 BYTEs	reserved
SeeAlso: #00817,#00983,#01011,#01034,#01046,#01049