Bitfields for AMD-645 IDE Drive Timing Control register:
Bit(s) Description )
31-28 primary drive 0 active DIOR#/DIOW# pulse width
27-24 primary drive 0 DIOR#/DIOW# recovery time (PCI clocks, less 1)
23-20 primary drive 1 active pulse width (PCI clocks, less 1)
19-16 primary drive 1 recovery time
15-12 secondary drive 0 active pulse width
11-8 secondary drive 0 recovery time
7-4 secondary drive 1 active pulse width
3-0 secondary drive 1 recover time (PCI clocks, less 1)
SeeAlso: #01034,#01042