Bitfields for AMD-645 IDE Miscellaneous Control 3 register:
Bit(s)	Description	)
 7	enable FIFO flush for read DMA on primary channel interrupt
 6	enable FIFO flush for read DMA on secondary channel interrupt
 5	enable FIFO flush for each sector on primary channel
 4	enable FIFO flush for each sector on secondary channel
 3-2	reserved
 1-0	maximum DRDY# pulse width
	00 unlimited
	01 64 PCI clocks
	10 128 PCI clocks
	11 192 PCI clocks
SeeAlso: #01034,#01038,#01039