Format of AMD-645 Peripheral Bus Controller, function 1 (IDE Control) data:
Offset Size Description )
00h 64 BYTEs header (see #00878)
(vendor ID 1106h [VIA Technologies], device ID 0571h)
09h BYTE programming interface
bit 7: Master IDE capability
bits 6-4: reserved (0)
bit 3: secondary channel supports operating mode selection
bit 2: use native PCI mode, not compatibility mode for sec. ch.
bit 1: primary channel supports operating mode selection
bit 0: use native PCI mode, not compatibility mode for pri. ch.
10h DWORD primary data/command base address
14h DWORD primary control/status base address
18h DWORD secondary data/command base address
1Ch DWORD secondary control/status base address
20h DWORD bus master control base address (default 0000CC01h)
40h BYTE chip enable (see #01035)
41h BYTE IDE configuration (see #01036)
42h BYTE reserved ("do not program")
43h BYTE FIFO configuration (see #01037)
44h BYTE miscellaneous control 1 (see #01038)
45h BYTE miscellaneous control 2 (see #01039)
46h BYTE miscellaneous control 3 (see #01040)
47h BYTE unused???
48h DWORD drive timing control (see #01041)
4Ch BYTE address setup time (see #01042)
4Dh BYTE reserved ("do not program")
4Eh BYTE secondary non-01F0h port access timing (see #01043)
4Fh BYTE primary non-01F0h port access timing (see #01043)
50h BYTE UltraDMA/33 extended timing control, Sec. Drive 1 (see #01044)
51h BYTE UltraDMA/33 extended timing control, Sec. Drive 0 (see #01044)
52h BYTE UltraDMA/33 extended timing control, Pri. Drive 1 (see #01044)
53h BYTE UltraDMA/33 extended timing control, Pri. Drive 0 (see #01044)
54h 4 BYTEs reserved
58h DWORD "reserved"
(appears to be an additional set of drive timing controls)
5Ch 4 BYTEs ???
60h WORD primary sector size (see #01045)
62h 6 BYTEs reserved
68h WORD secondary sector size (see #01045)
6Ah 150 BYTEs reserved
Note: the AMD-645 IDE controller is compatible with the SFF 8038i v1.0 spec
SeeAlso: #00817,#01011,#01046