Bitfields for AMD-640 ECC Control Register:
Bit(s) Description )
7 ECC mode select (0 = parity, 1 = ECC)
6 reserved (0)
5 assert SERR# for ECC multibit errors
4 assert SERR# for ECC single-bit errors
3 add 1T for SDRAM read cycles with ECC (required when ECC mode enabled)
2 enable ECC for banks 5 and 4
1 enable ECC for banks 3 and 2
0 enable ECC for banks 1 and 0
SeeAlso: #00983,#01003