X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Fri, 27 Apr 2012 10:50:55 -0700 From: Colin D Bennett To: geda-user AT delorie DOT com Subject: Re: [geda-user] Re: [coreboot] Dual SPI Flash adapter attempt 2.0 Message-ID: <20120427105055.224822b7@svelte> In-Reply-To: <4F9A67B3.9020908@schinagl.nl> References: <4F915B7C DOT 9000009 AT schinagl DOT nl> <4F959E1F DOT 6010803 AT schinagl DOT nl> <4F997E2E DOT 7010306 AT schinagl DOT nl> <4F99CEFD DOT 10707 AT schinagl DOT nl> <20120427000813 DOT 26333 DOT qmail AT stuge DOT se> <4F9A67B3 DOT 9020908 AT schinagl DOT nl> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator297.hostgator.com X-AntiAbuse: Original Domain - delorie.com X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - gibibit.com X-BWhitelist: no X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: c-67-160-113-82.hsd1.wa.comcast.net (svelte) [67.160.113.82]:35401 X-Source-Auth: colin AT gibibit DOT com X-Email-Count: 2 X-Source-Cap: c2t5bGVuO3NreWxlbjtnYXRvcjI5Ny5ob3N0Z2F0b3IuY29t Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Fri, 27 Apr 2012 11:32:35 +0200 Oliver Schinagl wrote: > Wow, nice big review :D feedback! > > On 04/27/12 02:08, Peter Stuge wrote: > > Oliver Schinagl wrote: > >> So the big question is; shall I send this to seeed for > >> fabrication or does it need some big change? > > > > The RN has slivers of soldermask between pads. Avoid this; it's > > too thin to work at all in production and the component size is > > so small that you want to avoid any chance of soldermask > > getting in the way of soldering. Board production processes are > > not exact, they are messy mechanically and chemically, and you > > should never push your producer's limits. If their limit is 6 > > never use less than 8. > That's just how the part comes. I haven't made or modified it. Is > there some way to increase soldermask spacing or better yet, so > set up some minimal with? To change the solder mask gap around pads: 1. Select the element by clicking it. 2. Make the 'solder mask' layer visible by clicking its swatch in the layer palette. (This causes the 'changeclearsize' command to operate on the solder mask openings instead of on polygon clearance... an ugly hack, so be aware this command behaves differently depending on whether 'solder mask' layer is visible. 3. Hit ':' and execute the command: changeclearsize(selected,0.1mil) (this basically resets the mask opening size) 4. Execute the command: minmaskgap(selected,1.5mil) (this will set the gap between copper and solder mask, but only will enlarge the gap so you need step 3 first). You can hover over the SMD pad and hit Ctrl+r to see the solder mask gap. > Their limit is 6, i've designed the board entirely using 8; > however the U3 part, the FET switch just comes in this size, or > smaller and would thus be impossible to use. > > > > > The SMD ICs and RN all have the package outline on silk > > absolutely tight around the soldermask apertures. Avoid this, > > again because the silk is way too close to the pads, and you > > never want silk anywhere outside the solder mask. Will the PCB fab house automatically remove silk from regions too close to holes in solder mask? Laen's PCB fab does this, so I am sloppy and use silk screen tighter than is actually producible, for layout assistance (I wish pcb had some extra virtual layers in footprints like "placement courtyard", "keepout", etc. so we didn't have to abuse the silk screen for everything). Regards, Colin