X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient: geda-user AT delorie DOT com
Date: Fri, 18 Nov 2011 05:38:39 -0500
From: gene glick <geneglick AT optonline DOT net>
Subject: Re: [geda-user] Modern GAL/PAL design with gEDA?
In-reply-to: <20111117225359.2fcf159a@rainbird>
To: geda-user AT delorie DOT com
Cc: Vanessa Ezekowitz <vanessaezekowitz AT gmail DOT com>
Message-id: <4EC635AF.2060104@optonline.net>
MIME-version: 1.0
Content-type: text/plain; charset=ISO-8859-1; format=flowed
Content-transfer-encoding: 7BIT
References: <20111117204524 DOT 10e586f5 AT rainbird> <4EC5CBEE DOT 5060904 AT optonline DOT net>
 <20111117225359 DOT 2fcf159a AT rainbird>
User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.15) Gecko/20110323
 Thunderbird/3.1.9
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com
Precedence: bulk


>without anything suggesting the type of chip the file is actually targeted at,
 >and nothing declaring how the internal signals are mapped to the 
device's pins.
 >

Your verilog code won't say any of that. The first level design entry is 
more or less, functional (this is what makes the code portable from chip 
vendor A to chip vendor B). Even though you are drawing a schematic in 
this case, and trying to output verilog - the verilog code will replace 
the explicit wires you drew with logical 'implied' connections, which 
all the backend tools understand.  Sort of like:
A = some output
B = some input
C = some input
A = B or D;

The backend stuff understands that the input pin B and C are connected 
to some OR gate.

Chip and pin assignment happen with the manufactures tools, either 
through gui or configuration files - your choice.

In the past, I have used Aldec Active-HDL, which is a really great tool, 
for design entry (vhdl, verilog and/or schematic). It then interfaces 
with Altera or Xilinx or Lattice in a way that you don't have to know 
the backend tools at all. Nice.

Lately, I have been using Icarus Verilog and GTKWave to simulate 
designs.  When satisfied with the results, move onto the Altera or 
Xilinx stuff.  So now I have to learn the backend tools - but for the 
simple stuff, it's simple enough.