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Date: Mon, 3 Nov 2014 10:31:22 -0800
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Subject: Re: [geda-user] Eagle's XML Format -> gEDA Schematic/PCB?
From: Ouabache Designworks <z3qmtr45 AT gmail DOT com>
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So I randomly picked one part from the pdf and found that it is contained
in two separate sections in the xml file:


<symbol name="TC4424AVPA">
<pin name="VDD" x="-17.78" y="7.62" length="middle" direction="pwr"/>
<pin name="IN_A" x="-17.78" y="2.54" length="middle" direction="in"/>
<pin name="IN_B" x="-17.78" y="0" length="middle" direction="in"/>
<pin name="NC_2" x="-17.78" y="-5.08" length="middle" direction="nc"/>
<pin name="NC" x="-17.78" y="-7.62" length="middle" direction="nc"/>
<pin name="GND" x="-17.78" y="-12.7" length="middle" direction="pas"/>
<pin name="OUT_A" x="17.78" y="7.62" length="middle" direction="out"
rot="R180"/>
<pin name="OUT_B" x="17.78" y="5.08" length="middle" direction="out"
rot="R180"/>
<wire x1="-12.7" y1="12.7" x2="-12.7" y2="-17.78" width="0.1524"
layer="94"/>
<wire x1="-12.7" y1="-17.78" x2="12.7" y2="-17.78" width="0.1524"
layer="94"/>
<wire x1="12.7" y1="-17.78" x2="12.7" y2="12.7" width="0.1524" layer="94"/>
<wire x1="12.7" y1="12.7" x2="-12.7" y2="12.7" width="0.1524" layer="94"/>
<text x="-4.0894" y="14.8844" size="2.0828" layer="95" ratio="10"
rot="SR0">&gt;NAME</text>
<text x="-5.7912" y="-22.2504" size="2.0828" layer="96" ratio="10"
rot="SR0">&gt;VALUE</text>
</symbol>

and


<deviceset name="TC4424AVPA">
<description>Dual High-Speed Power MOSFET Drivers</description>
<gates>
<gate name="A" symbol="TC4424AVPA" x="0" y="0"/>
</gates>
<devices>
<device name="" package="DIP254P762X533-8">
<connects>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="IN_A" pad="2"/>
<connect gate="A" pin="IN_B" pad="4"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="NC_2" pad="1"/>
<connect gate="A" pin="OUT_A" pad="7"/>
<connect gate="A" pin="OUT_B" pad="5"/>
<connect gate="A" pin="VDD" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="DESCRIPTION" value="MOSFET" constant="no"/>
<attribute name="MPN" value="TC4424AVPA" constant="no"/>
<attribute name="OC_FARNELL" value="1332308" constant="no"/>
<attribute name="OC_NEWARK" value="34M8777" constant="no"/>
<attribute name="PACKAGE" value="PDIP-8" constant="no"/>
<attribute name="SUPPLIER" value="Microchip" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>


parsing this out would be easy enough and you could regurgitate it back out
into a file named  something like element13/MOSFET/TC4424AVPA/PDIP-8.sym

Somebody will need to come up with an algorithm for the file name and how
to map everything into geda format.

John Eaton





On Mon, Nov 3, 2014 at 9:47 AM, Jason White <
whitewaterssoftwareinfo AT gmail DOT com> wrote:

> Hello, I just recently learned that newer versions of Eagle use an
> entirely XML based format for their Part Libraries as well as for
> schematic pages and layouts. Has anyone been able to do anything with
> this (maybe have written a script or something?) to allow gEDA to be
> able to use the rather large component libraries that have been
> produced and is freely distributed for Eagle?
>
> Take [1] for an example of such a library, it contains an enormous
> number [>1000] of pre-made symbols and footprints. Element14 as well
> as many others freely distribute part libraries to promote their
> services.
>
> It would be a time saver to be able to use those libraries in gEDA
> designs, either to extract individual symbols and packages, or perhaps
> even to have something represent the entire library file as a
> directory of symbols and footprints to gEDA.
>
> [1]
> http://www.element14.com/community/servlet/JiveServlet/download/64255-1-101093/Microchip.zip
>
> Thanks,
> Jason White
>

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Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><div>So I randomly picked one part from the pdf and found =
that it is contained in two separate sections in the xml file:<br><br><br>&=
lt;symbol name=3D&quot;TC4424AVPA&quot;&gt;<br>&lt;pin name=3D&quot;VDD&quo=
t; x=3D&quot;-17.78&quot; y=3D&quot;7.62&quot; length=3D&quot;middle&quot; =
direction=3D&quot;pwr&quot;/&gt;<br>&lt;pin name=3D&quot;IN_A&quot; x=3D&qu=
ot;-17.78&quot; y=3D&quot;2.54&quot; length=3D&quot;middle&quot; direction=
=3D&quot;in&quot;/&gt;<br>&lt;pin name=3D&quot;IN_B&quot; x=3D&quot;-17.78&=
quot; y=3D&quot;0&quot; length=3D&quot;middle&quot; direction=3D&quot;in&qu=
ot;/&gt;<br>&lt;pin name=3D&quot;NC_2&quot; x=3D&quot;-17.78&quot; y=3D&quo=
t;-5.08&quot; length=3D&quot;middle&quot; direction=3D&quot;nc&quot;/&gt;<b=
r>&lt;pin name=3D&quot;NC&quot; x=3D&quot;-17.78&quot; y=3D&quot;-7.62&quot=
; length=3D&quot;middle&quot; direction=3D&quot;nc&quot;/&gt;<br>&lt;pin na=
me=3D&quot;GND&quot; x=3D&quot;-17.78&quot; y=3D&quot;-12.7&quot; length=3D=
&quot;middle&quot; direction=3D&quot;pas&quot;/&gt;<br>&lt;pin name=3D&quot=
;OUT_A&quot; x=3D&quot;17.78&quot; y=3D&quot;7.62&quot; length=3D&quot;midd=
le&quot; direction=3D&quot;out&quot; rot=3D&quot;R180&quot;/&gt;<br>&lt;pin=
 name=3D&quot;OUT_B&quot; x=3D&quot;17.78&quot; y=3D&quot;5.08&quot; length=
=3D&quot;middle&quot; direction=3D&quot;out&quot; rot=3D&quot;R180&quot;/&g=
t;<br>&lt;wire x1=3D&quot;-12.7&quot; y1=3D&quot;12.7&quot; x2=3D&quot;-12.=
7&quot; y2=3D&quot;-17.78&quot; width=3D&quot;0.1524&quot; layer=3D&quot;94=
&quot;/&gt;<br>&lt;wire x1=3D&quot;-12.7&quot; y1=3D&quot;-17.78&quot; x2=
=3D&quot;12.7&quot; y2=3D&quot;-17.78&quot; width=3D&quot;0.1524&quot; laye=
r=3D&quot;94&quot;/&gt;<br>&lt;wire x1=3D&quot;12.7&quot; y1=3D&quot;-17.78=
&quot; x2=3D&quot;12.7&quot; y2=3D&quot;12.7&quot; width=3D&quot;0.1524&quo=
t; layer=3D&quot;94&quot;/&gt;<br>&lt;wire x1=3D&quot;12.7&quot; y1=3D&quot=
;12.7&quot; x2=3D&quot;-12.7&quot; y2=3D&quot;12.7&quot; width=3D&quot;0.15=
24&quot; layer=3D&quot;94&quot;/&gt;<br>&lt;text x=3D&quot;-4.0894&quot; y=
=3D&quot;14.8844&quot; size=3D&quot;2.0828&quot; layer=3D&quot;95&quot; rat=
io=3D&quot;10&quot; rot=3D&quot;SR0&quot;&gt;&amp;gt;NAME&lt;/text&gt;<br>&=
lt;text x=3D&quot;-5.7912&quot; y=3D&quot;-22.2504&quot; size=3D&quot;2.082=
8&quot; layer=3D&quot;96&quot; ratio=3D&quot;10&quot; rot=3D&quot;SR0&quot;=
&gt;&amp;gt;VALUE&lt;/text&gt;<br>&lt;/symbol&gt;<br><br></div>and<br><br><=
div><br>&lt;deviceset name=3D&quot;TC4424AVPA&quot;&gt;<br>&lt;description&=
gt;Dual High-Speed Power MOSFET Drivers&lt;/description&gt;<br>&lt;gates&gt=
;<br>&lt;gate name=3D&quot;A&quot; symbol=3D&quot;TC4424AVPA&quot; x=3D&quo=
t;0&quot; y=3D&quot;0&quot;/&gt;<br>&lt;/gates&gt;<br>&lt;devices&gt;<br>&l=
t;device name=3D&quot;&quot; package=3D&quot;DIP254P762X533-8&quot;&gt;<br>=
&lt;connects&gt;<br>&lt;connect gate=3D&quot;A&quot; pin=3D&quot;GND&quot; =
pad=3D&quot;3&quot;/&gt;<br>&lt;connect gate=3D&quot;A&quot; pin=3D&quot;IN=
_A&quot; pad=3D&quot;2&quot;/&gt;<br>&lt;connect gate=3D&quot;A&quot; pin=
=3D&quot;IN_B&quot; pad=3D&quot;4&quot;/&gt;<br>&lt;connect gate=3D&quot;A&=
quot; pin=3D&quot;NC&quot; pad=3D&quot;8&quot;/&gt;<br>&lt;connect gate=3D&=
quot;A&quot; pin=3D&quot;NC_2&quot; pad=3D&quot;1&quot;/&gt;<br>&lt;connect=
 gate=3D&quot;A&quot; pin=3D&quot;OUT_A&quot; pad=3D&quot;7&quot;/&gt;<br>&=
lt;connect gate=3D&quot;A&quot; pin=3D&quot;OUT_B&quot; pad=3D&quot;5&quot;=
/&gt;<br>&lt;connect gate=3D&quot;A&quot; pin=3D&quot;VDD&quot; pad=3D&quot=
;6&quot;/&gt;<br>&lt;/connects&gt;<br>&lt;technologies&gt;<br>&lt;technolog=
y name=3D&quot;&quot;&gt;<br>&lt;attribute name=3D&quot;DESCRIPTION&quot; v=
alue=3D&quot;MOSFET&quot; constant=3D&quot;no&quot;/&gt;<br>&lt;attribute n=
ame=3D&quot;MPN&quot; value=3D&quot;TC4424AVPA&quot; constant=3D&quot;no&qu=
ot;/&gt;<br>&lt;attribute name=3D&quot;OC_FARNELL&quot; value=3D&quot;13323=
08&quot; constant=3D&quot;no&quot;/&gt;<br>&lt;attribute name=3D&quot;OC_NE=
WARK&quot; value=3D&quot;34M8777&quot; constant=3D&quot;no&quot;/&gt;<br>&l=
t;attribute name=3D&quot;PACKAGE&quot; value=3D&quot;PDIP-8&quot; constant=
=3D&quot;no&quot;/&gt;<br>&lt;attribute name=3D&quot;SUPPLIER&quot; value=
=3D&quot;Microchip&quot; constant=3D&quot;no&quot;/&gt;<br>&lt;/technology&=
gt;<br>&lt;/technologies&gt;<br>&lt;/device&gt;<br>&lt;/devices&gt;<br>&lt;=
/deviceset&gt;<br><br><br></div><div>parsing this out would be easy enough =
and you could regurgitate it back out into a file named=C2=A0 something lik=
e element13/MOSFET/TC4424AVPA/PDIP-8.sym</div><div><br></div><div>Somebody =
will need to come up with an algorithm for the file name and how to map eve=
rything into geda format.<br><br></div><div>John Eaton<br><br><br></div><di=
v><br><br></div></div><div class=3D"gmail_extra"><br><div class=3D"gmail_qu=
ote">On Mon, Nov 3, 2014 at 9:47 AM, Jason White <span dir=3D"ltr">&lt;<a h=
ref=3D"mailto:whitewaterssoftwareinfo AT gmail DOT com" target=3D"_blank">whitewat=
erssoftwareinfo AT gmail DOT com</a>&gt;</span> wrote:<br><blockquote class=3D"gma=
il_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-lef=
t:1ex">Hello, I just recently learned that newer versions of Eagle use an<b=
r>
entirely XML based format for their Part Libraries as well as for<br>
schematic pages and layouts. Has anyone been able to do anything with<br>
this (maybe have written a script or something?) to allow gEDA to be<br>
able to use the rather large component libraries that have been<br>
produced and is freely distributed for Eagle?<br>
<br>
Take [1] for an example of such a library, it contains an enormous<br>
number [&gt;1000] of pre-made symbols and footprints. Element14 as well<br>
as many others freely distribute part libraries to promote their<br>
services.<br>
<br>
It would be a time saver to be able to use those libraries in gEDA<br>
designs, either to extract individual symbols and packages, or perhaps<br>
even to have something represent the entire library file as a<br>
directory of symbols and footprints to gEDA.<br>
<br>
[1] <a href=3D"http://www.element14.com/community/servlet/JiveServlet/downl=
oad/64255-1-101093/Microchip.zip" target=3D"_blank">http://www.element14.co=
m/community/servlet/JiveServlet/download/64255-1-101093/Microchip.zip</a><b=
r>
<br>
Thanks,<br>
Jason White<br>
</blockquote></div><br></div>

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