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Message-ID: <1382899880.21120.7.camel@pcjc2lap>
Subject: Re: [geda-user] Power to ICs with numslots > 1
From: Peter Clifton <pcjc2 AT cam DOT ac DOT uk>
To: geda-user AT delorie DOT com
Date: Sun, 27 Oct 2013 18:51:20 +0000
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On Sun, 2013-10-27 at 21:16 +0430, James Jackson wrote:
> Further to this, looking in the PCB Netlist dialog, I see that each of
> my subcircuits also contains duplicate nets (i.e. for +15v, 0v etc).
> 
> 
> How can I get gsch2pcb to merge given nets (as well as ICs, as above)
> across subcircuits?
> 

Looking at when I've done this in the past, I've manually exported power
rails by connecting the appropriate power symbol to an IO export at the
child level hierarchy level.

IMO, connecting the hierarchy explicitly is superior (and less prone to
errors) than trying to use flat net-names across the whole design.

In that case, you might as well use a flat design, especially as it
removes your ability to annotate nets with names in sub-circuits without
connecting all such sub-circuits together!


When I've been forced to strip out hierarchical names from a design for
layout refdes, there was a kludge I implemented to map gschem logical
refdes (X1/X3/R1) into a board specific refdes, such as R199.

The kludge is a non-standard patch (to gnetlist), and requires a file of
mappings between the hierarchical and board-level names. If you think it
might be of use, I can point you in the right direction to try it.


Could you explain the use-case you have for hierarchy, and roughly how
many instances of a given circuit you're using?

There might be easier ways to achieve what you want. In the past, for a
handful of channels, I've used a "master" schematic which is then
copied, and renumbered in a Makefile to produce the source-files for
netlisting.


Regards,

-- 
Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>

Clifton Electronics