X-Authentication-Warning: delorie.com: mail set sender to geda-help-bounces using -f X-Recipient: geda-help AT delorie DOT com X-SourceIP: 95.97.163.245 X-Authenticated-Sender: b DOT mykendevelopment AT upcmail DOT nl Message-ID: <55B606D7.7090605@iae.nl> Date: Mon, 27 Jul 2015 12:24:23 +0200 From: myken User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: geda-help AT delorie DOT com Subject: Re: [geda-help] Strategy of adding netname attributes in gSchem? References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Reply-To: geda-help AT delorie DOT com Hello, Please take an other look at your schematics. All nets with the same name will be tied together. Looking at your schematic I see two nets with the name C and two nets with the name Q that probably shouldn't be connected to each-other. So net C connected to pin 1 of U1 will be short-circuit to net C connected to pin 3 of U1, is that what you want? Cheers Robert. On 27/07/15 10:50, Csányi Pál (csanyipal AT gmail DOT com) [via geda-help AT delorie DOT com] wrote: > Hello, > > I'm working on my little mosquito repellent project. > So far I have the schematic completed ( see attachment ). > What did I furter to get the pcb? > > I create a new empty pcb with pcb application. > After that I run gsch2pcb on project file: > gsch2pcb tervezet > > ---------------------------------- > Done processing. Work performed: > 9 file elements and 0 m4 elements added to > KornyezetKimeloSzunyogRiaszto.new.pcb. > > Next steps: > 1. Run pcb on your file KornyezetKimeloSzunyogRiaszto.pcb. > 2. From within PCB, select "File -> Load layout data to paste buffer" > and select KornyezetKimeloSzunyogRiaszto.new.pcb to load the new > footprints into your existing layout. > 3. From within PCB, select "File -> Load netlist file" and select > KornyezetKimeloSzunyogRiaszto.net to load the updated netlist. > > 4. From within PCB, enter > > :ExecuteFile(KornyezetKimeloSzunyogRiaszto.cmd) > > to update the pin names of all footprints. > > But what I did is far from perfect; the resulted ratnest's are wrong. > > So what is the preferred way - or strategy - to set up netnames so so > one can get proper pcb layout at the and? >