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From:	"Chad Parker (parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date:	Mon, 5 Oct 2020 09:55:36 -0400
Message-ID:	<CAJZxidAyVxuLiUwxWz2zhTX6DVsMNr4qGOw+6EDM9c0mV5=_iQ@mail.gmail.com>
Subject:	Re: [geda-user] PCB connect pad to plane
To:	geda-user AT delorie DOT com
Reply-To:	geda-user AT delorie DOT com

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If you set the clearance of a pad to zero inside a polygon, you should get
a "Pad with insufficient clearance inside polygon" error, not a "copper
areas too close error". If you're getting the latter, that's a bug and we
should fix it. Are you building from source? Have you run the tests? The
DRC now has a pretty comprehensive set of test cases, and I would expect
this to be flagged. A quick test with 4.2.0 on Win10 flags this correctly.

It should, however, throw an error. It is technically breaking a design
rule, even if you're doing it intentionally. The consequences of making
such a connection unintentionally is quite high, and so it's safer, IMO, to
throw the error and have you verify that the connection is intentional.

Yes... we need more flexibility here. I'm aware. Also, SM pad thermals are
high on my priority list, the availability of which I would expect to make
this a non-issue.

--Chad

On Sun, Oct 4, 2020 at 12:55 AM Britton Kerin (britton DOT kerin AT gmail DOT com)
[via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

> Unfortunately the DRC will still
> report a violation for the pad, but this warning can be ignored.
> Incidentally, is it really correct to report "copper areas too close"
> when the clearance assigned to the pad in question is 0?  Perhaps this
> should be changed in pcb.
>

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<div dir=3D"ltr"><div>If you set the clearance of a pad to zero inside a po=
lygon, you should get a &quot;Pad with insufficient clearance inside polygo=
n&quot; error, not a &quot;copper areas too close error&quot;. If you&#39;r=
e getting the latter, that&#39;s a bug and we should fix it.=20
Are you building from source? Have you run the tests? The DRC now has a pre=
tty comprehensive set of test cases, and I would expect this to be flagged.=
 A quick test with 4.2.0 on Win10 flags this correctly.=C2=A0

</div><div><br></div><div>It should, however, throw an error. It is technic=
ally breaking a design rule, even if you&#39;re doing it intentionally. The=
 consequences of making such a connection unintentionally is quite high, an=
d so it&#39;s safer, IMO, to throw the error and have you verify that the c=
onnection is intentional.<br></div><div><br></div><div>Yes... we need more =
flexibility here. I&#39;m aware. Also, SM pad thermals are high on my prior=
ity list, the availability of which I would expect to make this a non-issue=
.<br></div><div></div><div><br></div><div>--Chad<br></div><div><br></div><d=
iv class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Sun, Oct =
4, 2020 at 12:55 AM Britton Kerin (<a href=3D"mailto:britton DOT kerin AT gmail DOT co=
m">britton DOT kerin AT gmail DOT com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT co=
m">geda-user AT delorie DOT com</a>] &lt;<a href=3D"mailto:geda-user AT delorie DOT com">=
geda-user AT delorie DOT com</a>&gt; wrote:<br></div><blockquote class=3D"gmail_qu=
ote" style=3D"margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,20=
4);padding-left:1ex">Unfortunately the DRC will still<br>
report a violation for the pad, but this warning can be ignored.<br>
Incidentally, is it really correct to report &quot;copper areas too close&q=
uot;<br>
when the clearance assigned to the pad in question is 0?=C2=A0 Perhaps this=
<br>
should be changed in pcb.<br>
</blockquote></div></div>

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