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Date:	Tue, 11 Jul 2017 06:28:23 +0200 (CEST)
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Subject:	Re: [geda-user] element restrictions: is it really about the file
	format? (was: Re: PCB, load element bug)
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FYI, the related pcb-rnd devlog entries:

My daydreaming from last year about how the data model could be cleaned up 
without a full rewrite:

http://repo.hu/projects/pcb-rnd/devlog/20160808_model.html

We are on track with this; step 1 and 2 are alerady finished, subcircuits 
span step 3 and 4. Had to insert an unforeseen step 2.5 for the layer 
rewrite.

My previous mail in this thread, converted to html, explaining why 
element restrictions exist and why it is not a file format question:

http://repo.hu/projects/pcb-rnd/devlog/20170711_elem.html

Some details on how the subcircuits-effort solves these problems:

http://repo.hu/projects/pcb-rnd/devlog/20170629_subc.html

Regards,

Igor2

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