Mail Archives: geda-user/2017/07/08/16:54:58
--Apple-Mail=_5FA6603C-882B-4ADF-B0DE-1997B6EB10ED
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=windows-1252
On Jul 6, 2017, at 2:04 AM, Vladimir Zhbanov (vzhbanov AT gmail DOT com) [via =
geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
> Hi, fellow gEDA users,
>=20
> I'm working on gnetlist refactoring in Lepton, trying to overpower its
> inherent issues. I have added some new tests revealing some of them.
> While pull request #139 at lepton issue tracker page [1] solves
> several of them (which I have still to document), there are others
> getting in my way. The PR is rewriting of gnetlist in Scheme (no C
> code anymore), the rewritten program is called `lepton-netlist', you
> can try it and report if ;-) / how it works on your system.
>=20
> Now, one of my ideas is to move mangling of hierarchy related
> attributes to the post-processing stage in order to process schematic
> pages and subpages separately, creating isolated subcircuits first.
Or keep the subcircuits isolated for hierarchical output.
>=20
> After some time of thinking, I realise the use cases when net=3D is
> mangled or not. The former case is for subcircuits that share their
> power sources, the latter is for such cases where such power sources
> are would-be-isolated within the subschematics.
Just power sources? Sometimes you have other global things like clocks, =
busses, =85
Scoping of names is tricky, depending on flow. One gotcha in ngspice is =
that GND is a hard-wired alias for node 0, so you can=92t have an =
isolated ground in a subcircuit unless you name it differently.
I haven=92t been unhappy to have explicit I/O connections on =
subcircuits. For ASIC work, the layout shop I work with insists on them, =
even for the substrate.
>=20
> Are there use cases where it is OK to use refdes=3D without mangling =
in
> flattened hierarchical schematic netlist? I see only a field for
> various potential conflicts=85
I=92ve cheated in the other direction, using a slot in a package on a =
lower level by referring to its partially mangled refdes. That fixed a =
special case, but the problem of slotting driving modularization has no =
general solution in the present logic.
>=20
> Thank you,
> Vladimir
>=20
> [1] https://github.com/lepton-eda/lepton-eda/pull/139
>=20
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
--Apple-Mail=_5FA6603C-882B-4ADF-B0DE-1997B6EB10ED
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename=signature.asc
Content-Type: application/pgp-signature;
name=signature.asc
Content-Description: Message signed with OpenPGP using GPGMail
-----BEGIN PGP SIGNATURE-----
Comment: GPGTools - https://gpgtools.org
iQIcBAEBCgAGBQJZYUXpAAoJEF1Aj/0UKykR3qIP/3TABtSa2ptiSZdH8eT2J7QG
loxtenT4PpcaBoIG+n3KuRxvx68hExwrAgPfQCnJRZaHI/B/i7YEhBaz9Hqmsn56
WotYAv0Ppcqm91fBXAV6m/MP5hQ1KLGHhWdirX8dKoEbfTecyYbp6kLr+b/PqNyR
shd7Lzp4IYNfLdLAnuMKnhBsXGHn7zu8KSlgTk92dCLLjj/XPARWFf/9PBFz+w6s
4smOdZwBTIrIT3ald7+MisZ1ptgNLvAKtK2AD1IPd8TkfSioXj2hQ3Y73Som6QjK
bdQix5YycTsrnFnmBCbQY9ZsWqBmuyga9CT1t2o1XyOq3/C5H/V+b9DXKP4uZYmt
rR4i0OA+6FgrNBCmJtfHtdpNOpDPuDtvmRiZVuBBGVVfZ0Fdwh62ajTww5YLt69g
bnDf6Bnv/NeRhAjFfXZ0dd/emnc0P8B5HXPTdM4WB6YATErWUVChORGDMaFKru5k
6TqeVawX0mw3x0BgZTp0kjja2t9rfwQG5qbCTrQ0aYBtHFbSw6FdGqBV+4aokJT2
+VD0peGE1wfjaihFWdB/5HoRdzNjWxhg06ZhoEHYaAevyctvp8yW+pSeuZzquvCV
KP/m/TGa/eazCJ5fAX9/jh6aPfA4M9ghOL4vf3+A2/h6Crjyq6OGZDiFvyXw7k2B
9lCgfLdnDSxY/GvqVA1+
=kAbC
-----END PGP SIGNATURE-----
--Apple-Mail=_5FA6603C-882B-4ADF-B0DE-1997B6EB10ED--
- Raw text -