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	Tue, 29 Dec 2015 12:21:04 -0800 (PST)
Date:	Tue, 29 Dec 2015 21:21:03 +0100
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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> For ASIC, these are similar to SPICE, I believe. In general, simulation to layout flows are hierarchical and ultimately based on the structural subset of the simulation language. But even in SPICE, you can decide to model a subcircuit behaviorally, and elementary models are always behavioral. So before layout, you may keep the option of simulating some blocks behaviorally for efficiency.
> 
> FPGA is similar: structural at high level, behavioral at low, but the boundary is more complicated.
> 
> After having written a makefile back end for gnetlist, I wonder about translating some sort of diagram into behavioral HDL code. The problems appear similar.
> 
> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd AT noqsi DOT com

At least gschem have flexibility. I made schematic where a "power" resistor was needed, just added a source attribute to get a subsheet with several resistors connected in series.

Nicklas Karlsson

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