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Tue, 29 Dec 2015 09:29:51 -0800 (PST) | |
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Date: | Tue, 29 Dec 2015 11:29:50 -0600 |
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Subject: | Re: [geda-user] Project leadership (design error in the core of gschem) |
From: | "Ozzy Lash (ozzy DOT lash AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
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--089e0103e6f6dcc90105280cc406 Content-Type: text/plain; charset=UTF-8 On Tue, Dec 29, 2015 at 10:39 AM, Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote: > > > slots: > The slotting mechanism is fundamentally worthless for a the majority > of cases were I would want to use it. Look at the 7400 symbols were > they have a whole extra symbol for the power pins. That is > conceptually IMHO something that should be a slot but you can't do > that because all symbols have to have the same number of pins and > geometry. > > In places were slotting could be cool we don't use it right in the > standard symbol library. Take the symbols for the larger xilinx chips. > I would rather each section of the chips I/O be it's own slot so I can > show the FPGA connections near what they are connected too instead of > putting the FPGA on it's own page (most of the time). Likewise > breaking it up into more symbols would mean not wasting most of a page > on the empty area inside the FPGA symbol. > > > I'm having a little trouble understanding what your definition of "slots" is. I think the current gschem concept of a slot is what I am used to, i.e. a slot is an interchangeable element of a chip. So a 7400 has 4 nand slots, and they are identical. As far as I am concerned, slots are only a tool for back annotation. During schematic capture, you can assign the gates from a chip in any order, then when laying out the PCB, you can choose which slot routes the best, and swap them around, and then back annotate. Bill --089e0103e6f6dcc90105280cc406 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable <div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo= te">On Tue, Dec 29, 2015 at 10:39 AM, Evan Foss (<a href=3D"mailto:evanfoss= @gmail.com">evanfoss AT gmail DOT com</a>) [via <a href=3D"mailto:geda-user AT delori= e.com">geda-user AT delorie DOT com</a>] <span dir=3D"ltr"><<a href=3D"mailto:g= eda-user AT delorie DOT com" target=3D"_blank">geda-user AT delorie DOT com</a>></span= > wrote:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;bo= rder-left:1px #ccc solid;padding-left:1ex"><br> <br> slots:<br> The slotting mechanism is fundamentally worthless for a the majority<br> of cases were I would want to use it. Look at the 7400 symbols were<br> they have a whole extra symbol for the power pins. That is<br> conceptually IMHO something that should be a slot but you can't do<br> that because all symbols have to have the same number of pins and<br> geometry.<br> <br> In places were slotting could be cool we don't use it right in the<br> standard symbol library. Take the symbols for the larger xilinx chips.<br> I would rather each section of the chips I/O be it's own slot so I can<= br> show the FPGA connections near what they are connected too instead of<br> putting the FPGA on it's own page (most of the time). Likewise<br> breaking it up into more symbols would mean not wasting most of a page<br> on the empty area inside the FPGA symbol.<br> <br><br></blockquote><div><br></div><div>I'm having a little trouble un= derstanding what your definition of "slots" is.=C2=A0 I think the= current gschem concept of a slot is what I am used to, i.e. a slot is an i= nterchangeable element of a chip.=C2=A0 So a 7400 has 4 nand slots, and the= y are identical.=C2=A0 As far as I am concerned, slots are only a tool for = back annotation.=C2=A0 During schematic capture, you can assign the gates f= rom a chip in any order, then when laying out the PCB, you can choose which= slot routes the best, and swap them around, and then back annotate. =C2=A0= <br><br></div><div><br></div><div>Bill <br></div></div></div></div> --089e0103e6f6dcc90105280cc406--
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