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Date: | Thu, 9 Jul 2015 15:45:21 -0400 |
Message-ID: | <CAM2RGhR3gk9z-5r2VZTC02JV4CDZr_RZd1wjjwX8Ut=+HUdHUg@mail.gmail.com> |
Subject: | Re: [geda-user] Back annotation |
From: | "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
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DJ ; I favour #2 for all the philisophical reasons I already mentioned plus the geda advantage over kicad is that it scales well to larger designs. gEDA should only be similar enought to share some libraries for moving content back and forth but not so similar that workflow and etc are the same, otherwise there is no point in having two parallel projects. On Thu, Jul 9, 2015 at 2:44 PM, John Griessen <john AT ecosensory DOT com> wrote: > On 07/09/2015 11:48 AM, John Doty wrote: >> >> For my ASIC designs, the parameter extracted netlists are about 200x the >> size of the netlists generated from the schematics. >> Printed circuit designs are generally flatter, but back-annotation into >> even a simple circuit still looks impractical to me. >> There’s really no utility to it anyway: the netlist is what you need as >> input for your verification process. > > > I can see how a 200x the lines of netlist result might stop you, but There > is always utility possible in scripting > the extraction of and reduction of raw data into a sum, with heuristics, for > sizing drive transistors - whether > in a chip logic fanout or a power supply. Perhaps you're stopping at the > netlist because of some detail > of your method, but reducing a flat layout extraction netlist to useful > annotations is the definition of utility to me. > And it doesn't bother me if that script is GUI button connected either. It > should be easy to change it is all. > Different strokes... > > -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/
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