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Date:	Thu, 09 Jul 2015 13:44:31 -0500
From:	John Griessen <john AT ecosensory DOT com>
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To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] Back annotation
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On 07/09/2015 11:48 AM, John Doty wrote:
> For my ASIC designs, the parameter extracted netlists are about 200x the size of the netlists generated from the schematics.
> Printed circuit designs are generally flatter, but back-annotation into even a simple circuit still looks impractical to me.
> There’s really no utility to it anyway: the netlist is what you need as input for your verification process.

I can see how a 200x the lines of netlist result might stop you, but There is always utility possible in scripting
the extraction of and reduction of raw data into a sum, with heuristics, for sizing drive transistors - whether
in a chip logic fanout or a power supply.  Perhaps you're stopping at the netlist because of some detail
of your method, but reducing a flat layout extraction netlist to useful annotations is the definition of utility to me.
And it doesn't bother me if that script is GUI button connected either.  It should be easy to change it is all.
Different strokes...

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