Mail Archives: geda-user/2015/02/16/17:35:05
Hello fellow free EDA users,
Has anyone here ever thought of a way to represent star connection
points in netlists fed to PCB? Imagine that there is a set of points
all of which are to be electrically connected together, so they look
like a single net, but the physical routing of this electrical
connection needs to follow a star topology. A typical example would
be two different kinds of ground which need to be connected at a
single point. Power supply nets also sometimes need this kind of
routing.
It seems to me that at least some of the proprietary EDA systems used
in the "professional" world support a feature whereby the two or more
"subnets" which are to be connected at a single point can be given
separate netnames and treated as separate nets in the schematics, and
then imported as such into the PCB layout tool. The latter then
understands the difference between these "subnets" and would flag an
error if a pin that's meant to connect to Digital_GND got connected to
Analog_GND instead - and yet at the same time treat the point at which
the two grounds do join as legitimate and not an erroneous short.
I know that some people solve this problem by inserting a physical 0R
jumper-resistor (or an inductor) between the different branches of a
power or ground net that needs to follow a star topology - and then
the nets are truly separate throughout the entire EDA flow. But this
approach has its own problems, as I shall illustrate:
Has anyone here heard of or used the legendary Openmoko phones?
Considering that both the Openmoko community and this one are about
freedom in some form, I figured there might be some intersection.
Does anyone remember the infamous bug #1024 that manifested in the
modem losing network registration and the device becoming unusable as
a phone? The bug had been traced to a poor layout in the modem
section, involving the traces that carry power from the power
management chip to the main digital ASIC.
The person who tracked that hardware bug down (Dieter Spaar) put the
blame on the LDO feedback trace (I presume he meant VSDBB), but I came
to a different conclusion: I believe that the 0R jumper-resistors are
to blame, the ones that have been put in the place of star connection
points. Look at the chipset vendor's original reference schematics:
ftp://ftp.ifctf.org/pub/GSM/Calypso/Leonardo_plus_quadband_schem.pdf
Look at the bottom of page 3 where the power connections are shown.
Notice how a power net named V-DBB exits the LDO regulator, goes by a
bypass cap (C214, placed near the LDO output), and then splits into
two "subnets" VDD-CORE and VDD-PLL via what the schematic drawing
depicts as "STAR_CONFIG" points.
Now look how Openmoko adapted this reference schematic design for
their modem application:
ftp://ftp.ifctf.org/pub/GSM/GTA02/GTA02_Schematic_MB_A5_1220.pdf
Look at page 16, again at the bottom. See how the "star points" have
been replaced with physical 0R resistors. And they really are
physical 0R jumper-resistors on the board: I looked at a physical
board to verify.
Apparently having the power supply current flow through these 0R
resistors and through the solder joints they come with turned out to
be a bad idea, and I suspect that these 0Rs are the real reason for
the infamous bug #1024. Had their EDA toolchain supported star points
without turning them into physical 0R jumpers, the problem would not
have occurred.
Fast-forwarding to the present, I am building my own GSM modem similar
to Openmoko's, based on the same TI Calypso chipset and the same
Leonardo reference design. (I also seek to make mine quadband instead
of triband, but that's besides the present issue.) I most certainly
do not wish to copy Om's bug #1024, so no 0R jumpers for me - I wish
to use proper star points in the PCB layout instead. In other words,
I would like to have the V-DBB net go from the Iota chip's VRDBB and
VSDBB balls (they are physically adjacent) to bypass cap C214, and then
from that bypass cap onward, have two separate "subnets" VDD_CORE and
VDD_PLL - and have these subnets go to their respective power consumers
(different sections of the Calypso chip fed via different balls) with
their respective bypass caps near the consumer.
And I want to have PCB understand what I'm doing - even though when
all copper connections are followed, VDD_CORE and VDD_PLL will form a
single electrical net with V-DBB, I want PCB to understand the
difference between them, so it will flag an error if a power ball on
the Calypso chip is connected to VDD_CORE when it should be VDD_PLL or
vice-versa. So I need to somehow convey to PCB that V-DBB, VDD_CORE
and VDD_PLL are 3 separate nets, yet it is not an error-short that
they physically join in the copper at some specific single point.
Would anyone here happen to have any ideas as to how this feat may be
accomplished in PCB? Would anyone perhaps happen to have a hacky
patch in their private fork that does what I seek or something similar?
Oh, and the "star point" at which the "subnets" join will very likely
need to be on an inner layer, not on the surface, or perhaps a specific
via may be designated as "the star point".
SF
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