Mail Archives: geda-user/2014/07/24/18:10:06
On 07/23/2014 04:32 PM, Evan Foss wrote:
> I figured array parts would be more like R01.001 or something but
> if you do away with refdes entirely for parts in the array life gets a
> lot easier. That said it still feels like an issue for post gschem
> stuff.
I'm not sure what you mean. Are you meaning netlist post processing?
Can't see that being effective...gschem is a visual tool, for the
parts that benefit from visual representation rather than just code chunks.
That usually means a wired module around a bunch of code chunks.
On 07/23/2014 04:50 PM, Dave Curtis wrote:> It appeared on plotted (micro-fiche vector art) schematic prints as a single block,
with a "36" displayed by breaking the bottom
> line of the ANSI-compliant schematic symbol and placing the text there. I'll try some ascii-art:
>
> +----+
> | |
> | +--OUT[0-31;P0-P3]
> | |
> +-36-+
>
> sorta like that, only prettier.
Yes, that's still the format for the chip design tools as of 13 years ago in 2001 when I last looked.
You *WANT* repeated elements that are identical -- so you can simulate enough of it to be sure.
On 07/23/2014 04:50 PM, Dave Curtis wrote:> So you could have one schematic, and experiment with different versions of the
attached attributes very easily (which was
> important for trying various place/route strategies in that day and age.)
Yes, that's still the aim in logic that has speed and to avoid race conditions. Have one schematic and
swap out pieces of layout to go with it, re-simulate to see if parasitics change the deal, rinse and repeat, etc...
All of this could become something to do again as cheap printable electronic materials come of age.
There are some automaton programs that can do sorta-kinda layout, but it still needs a junior engineer
on energy drinks to drive the simulate/respin/auto-route wash cycle of the high dollar tools.
And there are some integrations that will never be done in silicon because they'd never sell enough.
That washing machine door circuit to do almost everything the machine needs is an example. There won't
ever be a silicon planar fabbed chip for that since it is too small a market niche, and has power handling
and info handling in one.
- Raw text -