Mail Archives: geda-user/2014/07/06/00:42:10
On 2014-07-06 04:11:18 PM, Dave Curtis wrote:
> I'm working on a footprint where if I follow the data-sheet geometry and
> my normal design rules, I end up with a footprint where very skinny
> copper peninsulas sneak between pads when it is placed in a polygon.
> The peninsulas neck down to less than the minimum copper width rule.
>
> So, first off, I'm surprised that the Cu polygon allows Cu to pour into
> a space less than the minimum width rule.
>
> Secondly, I'm wondering if fab houses might flag that as a DRC violation
> even if pcb doesn't.
>
I have had a fab house complain about this. I ended up telling them to just
ignore it, and so far it hasn't been an issue but it does make me a little nervous,
particularly what might happen to fine slivers that get undercut during etching.
Also, I don't do RF stuff, so ending up with unconnected islands is not a issue for
me.
I have been meaning to write a polygon "bake" tool that fixes this, but have
been put off by the lack of a workable polygon library. Pretty much just needs
to erode then dilate by the minimum clearance. Was going to use shapely/GEOS
in python, but it's erosion doesn't seem to work :( So it went into the too hard
basket for the time being.
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