Mail Archives: geda-user/2013/03/13/05:41:01
Mike
Sorry for the delay in answering your questions.
We are a little weak on formal syntax documentation. Version 2.1 of the compiler does not require an explicit "include" statement. If the .phdl file is in the same directory it is included in the compile. You can however use package_name.part_name syntax when instantiating components to make sure you are putting down the part you want.
For the PHDL 3.0 rewrite one of the tasks is to develop very clear documentation on how to use the language and compiler. Right now that is a work in progress so I recommend that you look at this reference design that I did to test the compiler. This is the top level file and the other referenced files are in the same folder.
http://sourceforge.net/p/phdl/code/ci/d3b7ae84f9da971895569c093c74a7f0780f193a/tree/doc/refdesign/refboard.phdl
I like to put all the component definitions in a single file called devices.phdl
http://sourceforge.net/p/phdl/code/ci/d3b7ae84f9da971895569c093c74a7f0780f193a/tree/doc/refdesign/devices.phdl
The above reference design uses hierarchy. You define a "subdesign" with ports instead of just nets and those ports are used to connect to the next level up.
Our compiler does not care what you use as pin designators. The pin number is just an ascii string. The new 3.0 compiler will have full Unicode support so you can have Arabic pin numbers if you want.
The PHDL compiler generates a Bill of Materials (BOM) in .CSV format.
We anticipated the need to back-annotate reference designator changes by providing a control file that lists all the parts by hierarchical path and reference designator. If a part is in that file then the compiler uses that refdes. If not, it adds the part with a unique new refdes. You can modify that file to change part reference designators.
Personally, I don't like the idea of a layout tool changing my reference designators. On the other hand, we provide a unique new capability with respect to refdes strings. We allow the designer to provide a REFPREFIX attribute on subdesigns. If provided, the compiler prepends this string to the reference designator on the part. Eg., if you put REFPREFIX = "X" on your power supply subdesign then R17 in the power supply becomes XR17 in your netlist and BOM. This is optional but is nice because in the layout tool you can sort by refdes and get parts grouped together by subdesign.
It is on our ToDo list to make it easy to write a translator to at least one graphical tool. The 3.0 compiler will generate an intermediate format netlist PHDLIF that is designed to be easily converted into any format.
We are in deep re-write mode now but please join our PHDL mailing list on sourceforge.net. I hope we are setup on the wiki to accept participation. Then we can take PHDL discussions over there and not clutter the gEDA maillist. :-)
Peter Dudley
-----Original Message-----
From: Mike Crowe [mailto:mcrowe AT gcdataconcepts DOT com]
Sent: Monday, March 11, 2013 4:18 PM
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] PHDL to PCB conversion path?
On Thu, 2013-03-07 at 03:21 -0700, peter dudley wrote:
Greetings
I am very interested in your work! I too have problems with the scalability and maintainability of graphical programming languages.
I have a few questions after spending a few minutes on your site.
Is there a reference somewhere that describes the syntax a little more?
Specifically how would someone include a library of components (possibly "#include")? How do sub-circuits work? How do you handle non-numeric pin designators?
Schematic, layout, and BOM maintenance is a big issue for me. Is there a tool that allows attributes be back annotated from a database?
I'd like to see a tool that takes a gschem schematic and produces PHDL.
The work may be half done. I have existing tools that convert gschem files into XML documents. Is there a tool that takes XML and converts it to a PHDL?
As far as pushing PHDL to PCB, I think it would be pretty simple to implement with a PHDL->XML->XSLT->PCB chain. PCB artwork updates would probably be a little more difficult to implement, since components and nets need to be inserted and removed.
> Hello All,
>
> I am currently part of a small group of people developing a new
> Hardware Description Language (HDL) specifically for Printed Circuit
> Board (PCB) development. We call our language PHDL. It is a
> open-source project and you can find some information about it here if
> you are interested, http://sourceforge.net/p/phdl/wiki/Home/. We have
> written version 1 and version 2 of the PHDL compiler and quite a few
> utilities to support it.
>
> PHDL replaces schematic entry in the the PCB design flow. As such,
> our compiler must write out netlist files in the correct format for
> each layout tool we want to support. So far, PHDL 2.1 can write
> netlist files for Mentor PADS and CadSoft Eagle PCB. We are
> currently doing a rewrite of the PHDL compiler to improve
> maintainability and extensibility and we would very much like to
> write netlist files that are compatible with the gEDA/PCB layout tool.
>
> I am seeking advice here. Can anyone offer an opinion as to the best
> file format to write in order to get our netlist into the gEDA/PCB
> layout tool?
>
> I see gnetlist converts gEDA schematic files to something that
> geda/pcb can read. Does it make sense for us to write gEDA schematic files?
> Is there a simpler or more stable file format we should write to get
> into this open source layout tool.
>
> I also stumbled across a webpage for a gEDA Translate project but it
> looks to be just conceptual at this point.
>
> Anyway, all constructive advice is appreciated.
>
> Regards,
>
> Pete Dudley
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