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Mail Archives: geda-user/2013/02/15/13:50:11

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From: al davis <ad252 AT freeelectron DOT net>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] gnetlist extractor
Date: Fri, 15 Feb 2013 13:49:44 -0500
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On Wednesday 13 February 2013, bsalinux AT gmail DOT com wrote:
> I tried to do a gnucap simulation involving BS170 MOSFET and
> the extractor did not extract / interpret four contacts for
> the MOSFET as expected by GNUCAP.
> 
> What was extracted was:
> 
> M1  4 1 0 bs170
> 
> instead of (substrate connected to source)
> 
> M1  4 1 0 0 bs170
> 
> 
> According to gnucap, first  statement takes "BS170" as the
> substrate contact.

The spice, and spice compatible simulators, require 4 
connections for a mosfet.  The fourth one is the substrate.  If 
in doubt, and for all discrete 3-terminal mosfets, the substrate 
should be connected to the source.

But now look at the schematic, and how netlist extraction works.  
Whatever number of pins a device has on the schematic, that's 
how many it will have in the extracted netlist.  Therefore, any 
3-pin mosfet will give you an incorrect netlist.  The problem is 
in the symbol, or really using the wrong symbol for the 
application, not with the netlister.  You need to use a symbol 
that has 4 pins.

Exactly how this situation is handled by the simulator varies.

With gnucap, if you just list everything without delimeters, it 
will screw up in this case.  If you put the node list in 
parenthesis, it will give you a warning "need 1 more nodes", and 
try to guess what to do with the other one, (grounding it) often 
not the way you want.  Same goes for Verilog format netlists, 
where you can map the pins by name.

I don't know what ngspice does in this case, but since the 
"standard" says you need 4 pins, and you are missing one, you 
can't depend on anything in particular.

Again ... you need to use a mosfet symbol that has 4 pins.

Why is it this way?  I didn't make that decision, but remember 
SPICE is "Simulation Program with Integrated Circuit Emphasis" 
.. designed for chip designers.  They need to be concerned about 
the substrate.  The substrate is like a second gate, or "back 
gate".

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