Mail Archives: geda-user/2012/03/12/17:53:23
--Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ)
Content-type: text/plain; charset=UTF-8; format=flowed
Content-transfer-encoding: 7BIT
Content-disposition: inline
On Mon, Mar 12, 2012 at 3:15 PM, DJ Delorie wrote:
>> Someone mentioned "the zero-length trace problem" in private
>> email; what's up with that? I haven't googled it yet but I will in
>> a moment.
>
> If you have a trace that's so small as to be completely hidden under a
> pin or pad, with the "join" flag set, then if that trace will
> "connect" to a polygon even if the clearance around the pin/pad means
> it really doesn't.
>
> I.e. DRC doesn't consider pin clearance when checking to see if a
> trace connects to a polygon.
Yeah - you jogged my memory . I had a problem once with a shorted trace
- if I recall, it was a thermal that I added
on layer-1, by accident. The polygon attached to it when I didn't mean
to. Anyway, divide and conquer zeroed me in
on the problem. I may have looked at the .pcb file at that point for a
hint if it wasn't obvious on the gui.
Anyway - divide and conquer on a backed up version only :)
--Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ)
Content-type: text/html; charset=UTF-8
Content-transfer-encoding: quoted-printable
Content-disposition: inline
<FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KER=
NING=3D"0"><br></FONT><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" L=
ETTERSPACING=3D"0" KERNING=3D"0"><br></FONT><FONT FACE=3D"Verdana" SIZE=3D"=
2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0"><br></FONT><DIV ALIG=
N=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACIN=
G=3D"0" KERNING=3D"0">On Mon, Mar 12, 2012 at 3:15 PM, DJ Delorie wrote:</F=
ONT></DIV><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=
=3D"0" KERNING=3D"0"><br></FONT><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" =
SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> >&nb=
sp; Someone mentioned "the zero-length trace problem"=
in private</FONT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"=
2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> > email; wha=
t's up with that? I haven't googled it yet but I will in</FONT></DIV>=
<DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LET=
TERSPACING=3D"0" KERNING=3D"0">> > a moment.</FONT></DIV><DIV ALIGN=
=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=
=3D"0" KERNING=3D"0">> </FONT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Ve=
rdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> =
If you have a trace that's so small as to be completely hidden under a</FON=
T></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000=
000" LETTERSPACING=3D"0" KERNING=3D"0">> pin or pad, with the "join=
" flag set, then if that trace will</FONT></DIV><DIV ALIGN=3D"LEFT"><F=
ONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNI=
NG=3D"0">> "connect" to a polygon even if the clearance around=
the pin/pad means</FONT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" S=
IZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> it reall=
y doesn't.</FONT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2=
" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> </FONT></DIV><DI=
V ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTER=
SPACING=3D"0" KERNING=3D"0">> I.e. DRC doesn't consider pin clearance wh=
en checking to see if a</FONT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verda=
na" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">> tra=
ce connects to a polygon.</FONT></DIV><FONT FACE=3D"Verdana" SIZE=3D"2" COL=
OR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0"><br></FONT><DIV ALIGN=3D"L=
EFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0=
" KERNING=3D"0">Yeah - you jogged my memory . I had a problem once wi=
th a shorted trace - if I recall, it was a thermal that I added</FONT></DIV=
><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LE=
TTERSPACING=3D"0" KERNING=3D"0">on layer-1, by accident. The polygon attach=
ed to it when I didn't mean to. Anyway, divide and conquer zeroed me in</FO=
NT></DIV><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#00=
0000" LETTERSPACING=3D"0" KERNING=3D"0">on the problem. I may have looked a=
t the .pcb file at that point for a hint if it wasn't obvious on the =
gui.</FONT></DIV><FONT FACE=3D"Verdana" SIZE=3D"2" COLOR=3D"#000000" LETTER=
SPACING=3D"0" KERNING=3D"0"><br></FONT><DIV ALIGN=3D"LEFT"><FONT FACE=3D"Ve=
rdana" SIZE=3D"2" COLOR=3D"#000000" LETTERSPACING=3D"0" KERNING=3D"0">Anywa=
y - divide and conquer on a backed up version only :)</FONT></DIV>=
--Boundary_(ID_CB4VQ/ADhluBcPuuz2tjnQ)--
- Raw text -