delorie.com/archives/browse.cgi   search  
Mail Archives: geda-user/2012/02/20/01:21:35

X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
Date: Mon, 20 Feb 2012 01:21:22 -0500
Message-Id: <201202200621.q1K6LM19029205@envy.delorie.com>
From: DJ Delorie <dj AT delorie DOT com>
To: geda-user AT delorie DOT com
In-reply-to: <4F41DD58.8030607@optonline.net> (message from gene glick on Mon,
20 Feb 2012 00:42:48 -0500)
Subject: Re: [geda-user] verilog question - blocking/non-blocking
References: <4F41CB0A DOT 2020902 AT optonline DOT net>
<201202200517 DOT q1K5HrUD026271 AT envy DOT delorie DOT com> <4F41DD58 DOT 8030607 AT optonline DOT net>
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com

> I suppose the "=" (blocking) makes the code sequential,

NOT SEQUENTIAL.  Think "series wired".  "=" means "if the signal has
been re-defined by some previous logic, use that new output'd signal
as my input".  "<=" means "my inputs will always be the original
signals."

Remember, verilog is a SCHEMATIC.  It is NOT CODE.  It is wires and
gates and latches.  If you had a gschem page with wires and gates and
latches, you wouldn't expect each gate's output to be computed
sequentially, would you?

> but what the heck does the synthesis tool build?

the synthesis tool will probably create a circuit of combinatoric
gates connected in series to perform the logic you asked for.

I think it builds the same logic either way, the big difference is
when the value becomes valid relative to other signals.  If you're
using "=" you're going to be using the output of the combinatorics
directly, so you get some arbitrary propogation delay, which may cause
problems.  With "<=" it's delayed a clock, but the edges happen in
sync with all the other edges.

The problem with propogation delay, is you might not meet the setup
times for whoever uses those values.  At high clock speeds, you need
the latches to re-synchronize everything and reset the setup times vs
propogation delays.

> Wouldn't your method of 'previous count' and 'count' use twice as many 
> registers?

Don't confuse verilog "registers" with hardware "latches".  Registers
are just "values you can change" but they could easily be the output
of a NAND gate or even just a wire, not always a physical latch.

- Raw text -


  webmaster     delorie software   privacy  
  Copyright © 2019   by DJ Delorie     Updated Jul 2019