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Date:	Mon, 21 Nov 2011 13:48:05 -0500
Message-Id:	<201111211848.pALIm5Fk027021@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
In-reply-to:	<4ECA9BF9.9000601@ecosensory.com> (message from John Griessen on
	Mon, 21 Nov 2011 12:44:09 -0600)
Subject:	Re: [geda-user] Modern GAL/PAL design with gEDA?
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> Think of the convenience of verilog being about assignments that
> happen in parallel, and you'll be way ahead.

Verilog always confused me until I realized THEY'RE TALKING ABOUT
WIRES.  Electronics doesn't happen sequentially, neither does Verilog.
If you *do* ask for sequential steps, the compiler has to do extra
work to simulate that in hardware.

Just because it looks like C doesn't mean it acts like C.

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