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Date:	Thu, 17 Nov 2011 22:47:07 -0700
Message-ID:	<CAOtMX2jZvJQh9hFfsevKJyPimKtkSLgmQMHjHjrUhGyT9X-b3g@mail.gmail.com>
Subject:	Re: [geda-user] Modern GAL/PAL design with gEDA?
From:	asomers AT gmail DOT com
To:	geda-user AT delorie DOT com
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My advice is to download ispLever Class gratis from Latticesemi.com.
It's windows-only, but it's far more intuitive than either Altera's or
Xilinx's software.  It's fairly easy to set up a project, tell
ispLever what chip you want it to use, and either tell it the pin
assignments or have it make the assignments itself.

Unlike FPGAs, a GAL22V10 requires no special  secrets to program.  An
FAE once showed me how to decode the JEDEC file using publicly
available information.  So theoretically someone _could_ write an open
source compiler for it - but no one has.

-Alan

On Thu, Nov 17, 2011 at 8:53 PM, Vanessa Ezekowitz
<vanessaezekowitz AT gmail DOT com> wrote:
> On Thu, 17 Nov 2011 22:07:26 -0500
> gene glick <geneglick AT optonline DOT net> wrote:
>
>> - I see people designing things left and right using programmable logic
>> of one sort or another, some of which are of such complexity that it
>> would be next to impossible to do using just lists of logic equations.
>> >
>> > Whatever the case, I don't want to have to resort to using closed-source
>> > or proprietary software or operating systems to do any more of this than
>> > is absolutely necessary.
>> >
>>
>>
>> Regardless of your front-end design entry method, you will always use
>> closed-source proprietary tools for the back-end synthesis and
>> place/route.
>
> Well that part doesn't bother me too much - I expected that at least the final one or two steps would involve proprietary tools.  It's the process of getting from Gschem to the data those tools need that is lost on me.
>
>> So plan on using Xilinx or Altera or Lattice etc., no
>> matter what.  You can use vhdl or verilog as inputs to just about any of
>> these tools.
>
> I thought about using verilog, but this is where I've hit a brick wall - gnetlist is willing to generate a verilog file out of my schematic:
>
> gnetlist -v -o test.v -g verilog -O tpal cbr-refresh.sch
>
> ...but aside from the numbered-pin warnings I understand I can ignore, all the resultant file contains are lines declaring each instantiation of the various symbols, and a list of wires - but with what looks like an incorrect "model" line and without anything suggesting the type of chip the file is actually targeted at, and nothing declaring how the internal signals are mapped to the device's pins.  Nothing I've found on the web tells me how to set these parameters.
>
>> gschem -> gnetlist -> verilog -> programmable_logic_proprietary_tools
>
> This is the sort of workflow I expected actually, but the problem is finding newbie-friendly information on how to accomplish each step.
>
> --
> "There are some things in life worth obsessing over.  Most
> things aren't, and when you learn that, life improves."
> http://digitalaudioconcepts.com
> Vanessa Ezekowitz <vanessaezekowitz AT gmail DOT com>
>
>

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