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Date:	Thu, 17 Nov 2011 22:07:26 -0500
From:	gene glick <geneglick AT optonline DOT net>
Subject:	Re: [geda-user] Modern GAL/PAL design with gEDA?
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- I see people designing things left and right using programmable logic 
of one sort or another, some of which are of such complexity that it 
would be next to impossible to do using just lists of logic equations.
>
> Whatever the case, I don't want to have to resort to using closed-source or proprietary software or operating systems to do any more of this than is absolutely necessary.
>


Regardless of your front-end design entry method, you will always use 
closed-source proprietary tools for the back-end synthesis and 
place/route. So plan on using Xilinx or Altera or Lattice etc., no 
matter what.  You can use vhdl or verilog as inputs to just about any of 
these tools.  Although I have never tried this, it seems that gnetlist 
has a verilog and vhdl output mode.  Sounds exactly like what you are 
looking for.  Maybe some of the users can comment on how well it works.

gschem -> gnetlist -> verilog -> programmable_logic_proprietary_tools

Assuming that works, you will need the programming tools for the chip 
(burner, or in-circuit jtag, for example).

You should consider verilog.  4 FF and some logic would be a very short 
program to write.

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