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Date:	Mon, 7 Nov 2011 15:46:03 -0700
Message-ID:	<CAN0Jx--++wT-ik0wf5uYrswX0ogrPd7tRTkBu=agRLML+NO+TQ@mail.gmail.com>
Subject:	Re: [geda-user] PCIe card?
From:	Russell Dill <Russ DOT Dill AT asu DOT edu>
To:	geda-user AT delorie DOT com
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On Mon, Nov 7, 2011 at 3:08 PM, Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au> wrote:
> Hi Russell,
>
> On Tue, Nov 8, 2011 at 8:32 AM, Russell Dill <Russ DOT Dill AT asu DOT edu> wrote:
>> On Mon, Nov 7, 2011 at 2:23 PM, Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au> wrote:
>>> On Tue, Nov 8, 2011 at 8:04 AM, Russell Dill <Russ DOT Dill AT asu DOT edu> wrote:
>>>>> One idea I had for a quick start was to lay out and edit a PCB with
>>>>> the differential pairs replaced by fat single traces of thickness (2 *
>>>>> differential trace copper thickness + differential trace internal
>>>>> spacing).  A fairly simple bit of code could later convert these from
>>>>> fat single traces to differential pairs.
>>>>
>>>> BTW, it isn't really necessary to route differential traces this way.
>>>> Rather than route them with a very tightly regulated spacing, you can
>>>> route them instead with a minimum spacing as single ended traces,
>>>> which is much easier. Just be sure they have equal lengths impedances.
>>>
>>> That's how I presently use PCB to implement differential pairs.  It
>>> works well enough for the ~ 1Gbps signals that I'm working with, but I
>>> wouldn't try it for something like 5Gbps PCIE.
>>> The main limitation is that the spacing between the traces changes
>>> slightly for diagonal lines, changing the impedance.
>>
>> As long as you have them far enough apart, it doesn't matter if the
>> spacing changes.
>>
>>> For high speeds I'd also want to eliminate sharp corners and use arcs
>>> for every change in direction.  Creating pairs of arcs that maintain
>>> even spacing would be tedious using PCB's present UI.  Creating single
>>> thick arcs in the GUI and later having them transformed into correctly
>>> spaced pairs of arcs would be bearable.
>>
>> I don't think that'd have an effect even at 5Gpbs. You'd probably even
>> be ok with right angle corners, unless your margins are really really
>> tight already.
>
> That sounds rather optimistic to me :-)
>
> See p12 of:
>
> http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=6d37ec2f8543fc1f9d8ace6264d08b469f57e5f1
>
> (tiny URL in case the above gets broken in transit:)

I realise it says "no 90 bends", but they provide no numbers or
references for their recommendation, and they already have several 90
bends in their design. Every via is 2 90 bends. Every pad is 2 90
bends, every pin is 2 90 bends.

http://www.sigcon.com/Pubs/edn/bigbadbend.htm

There are several good right angle bend threads on si-list, here's a good one

http://www.freelists.org/post/si-list/PCB-Corners-Need-help-finding-research-paper

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