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| X-Recipient: | geda-user AT delorie DOT com |
| Date: | Mon, 13 Aug 2012 01:27:00 +0200 |
| From: | Kai-Martin Knaak <kmk AT familieknaak DOT de> |
| To: | <geda-user AT delorie DOT com> |
| Subject: | [geda-user] silk layer names |
| Message-ID: | <20120813012700.2106039c@akka> |
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The default layer stack as set by PCB for a new layout contains two silk
layers. Both of them bear the same name "silk". The name does not
actually show up in the GUI. Unless I am mistaken, the layer name of the
silk layers is not used anywhere in pcb except on save. Still, it is
irritating at manual edits of a pcb. In addition, the duplicate layer
name complicates scripted manipulation of the file.
The attached patch sets the default name to "top silk" and "bottom silk"
respectively. It is a rather simple patch. So I hope, it will be applied
soon.
---<)kaimartin(>---
--=20
Kai-Martin Knaak
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filename=0001-set-default-names-of-silk-layers.patch
=46rom f6cd4c8b79153886ceb4dd614538cfe5b9aa2863 Mon Sep 17 00:00:00 2001
From: Kai-Martin Knaak <kmk AT lilalaser DOT de>
Date: Mon, 13 Aug 2012 01:06:21 +0200
Subject: [PATCH] set default names of silk layers Currently, the names of t=
he
two silk layers are set to the exact same value. This patch
set their name to "top silk" and "bottom silk".
---
src/create.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/create.c b/src/create.c
index 9ed7caa..dd25ee5 100644
--- a/src/create.c
+++ b/src/create.c
@@ -223,8 +223,8 @@ CreateNewPCBPost (PCBType *pcb, int use_defaults)
if (ParseGroupString (Settings.Groups, &pcb->LayerGroups, DEF_LAYER))
return 1;
=20
- pcb->Data->Layer[component_silk_layer].Name =3D strdup ("silk");
- pcb->Data->Layer[solder_silk_layer].Name =3D strdup ("silk");
+ pcb->Data->Layer[component_silk_layer].Name =3D strdup ("top silk");
+ pcb->Data->Layer[solder_silk_layer].Name =3D strdup ("bottom silk");
}
return 0;
}
--=20
1.7.10.4
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