Mail Archives: geda-help/2014/06/25/10:20:06
--Apple-Mail=_795770C1-F7ED-4930-A1F4-56B9C0C05D10
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=windows-1252
On Jun 25, 2014, at 9:11 AM, James Battat <jbattat AT wellesley DOT edu> wrote:
> Hi folks,
>=20
> I'm a new user of gEDA and have successfully run some simulations of =
analog circuits with gschem --> gnetlist --> ngspice.
> I was looking online for tutorials about simulating logic circuits =
(e.g. a 4-bit counter) with gEDA, but did not find any. My goal is to =
generate timing diagrams that account for propagation delays in the =
individual chips (flip-flops and and/or gates in this case). =20
>=20
> Is this possible?
Yes.
You=92ll probably have to edit or create some symbols. Symbols in the =
standard distribution are primarily for layout, not simulation. The =
overloading of the pinseq attribute, used both for slotting and pin =
ordering in the netlist, can be trouble.
It=92s mainly a matter of getting the the underlying models right. =
Recent ngspice versions do mixed signal modeling natively. See Chapter =
12 of the ngspice manual. You can also use physical models based on =
transistors.
Resources:
http://ngspice.sourceforge.net/docs/ngspice-manual.pdf
http://www.brorson.com/gEDA/SPICE/intro.html (how to use the spice-sdb =
back end to gnetlist).
http://www.gedasymbols.org/user/john_doty/ (symbols for using Open-IP =
physical models in gEDA).
https://github.com/noqsi/gnet-spice-noqsi (a more flexible gnetlist back =
end for SPICE).
And finally, here=92s an example symbol for using Open-IP to physically =
model a 74AC00 via the spice-noqsi back end:
--Apple-Mail=_795770C1-F7ED-4930-A1F4-56B9C0C05D10
Content-Disposition: attachment;
filename=NAND.sym
Content-Type: application/octet-stream;
name="NAND.sym"
Content-Transfer-Encoding: 7bit
v 20130925 2
L 300 0 300 600 3 0 0 0 -1 -1
L 300 600 700 600 3 0 0 0 -1 -1
T 500 700 5 10 0 0 0 0 1
device=CD74AC00M96
T 500 900 5 10 0 0 0 0 1
slot=1
T 500 1100 5 10 0 0 0 0 1
numslots=4
T 500 1300 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 500 1500 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 500 1700 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 500 1900 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 300 0 700 0 3 0 0 0 -1 -1
A 700 300 300 270 180 3 0 0 0 -1 -1
V 1050 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1100 300 1300 300 1 0 1
{
T 1100 350 5 8 1 1 0 0 1
pinnumber=3
T 1100 250 5 8 0 1 0 2 1
pinseq=3
T 950 300 9 8 0 1 0 6 1
pinlabel=Y
T 950 300 5 8 0 1 0 8 1
pintype=out
}
P 300 100 0 100 1 0 1
{
T 200 150 5 8 1 1 0 6 1
pinnumber=2
T 200 50 5 8 0 1 0 8 1
pinseq=2
T 350 100 9 8 0 1 0 0 1
pinlabel=B
T 350 100 5 8 0 1 0 2 1
pintype=in
}
P 300 500 0 500 1 0 1
{
T 200 550 5 8 1 1 0 6 1
pinnumber=1
T 200 450 5 8 0 1 0 8 1
pinseq=1
T 350 500 9 8 0 1 0 0 1
pinlabel=A
T 350 500 5 8 0 1 0 2 1
pintype=in
}
T 300 700 8 10 1 1 0 0 1
refdes=U?
T 500 2050 5 10 0 0 0 0 1
footprint=SO14
T 500 2250 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 2000 1100 8 10 0 1 0 0 4
spice-prototype=X1? #1 #2 #3 #7 #14 NAND
X2? #4 #5 #6 #7 #14 NAND
X3? #9 #10 #8 #7 #14 NAND
X4? #12 #13 #11 #7 #14 NAND
--Apple-Mail=_795770C1-F7ED-4930-A1F4-56B9C0C05D10
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=us-ascii
=20
> =20
>=20
> According to the following thread, in 2001 it was not possible to run =
logic simulations in gEDA:
> http://archives.seul.org/geda/user/Sep-2001/msg00001.html
>=20
> If someone has an example of running a logic simulation (e.g. =
flip-flops clocked by an oscillator) that would be greatly appreciated.
>=20
> If it's not possible to do this in gEDA, could you recommend free =
tools that do this?
>=20
> Thanks,
> James
>=20
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
--Apple-Mail=_795770C1-F7ED-4930-A1F4-56B9C0C05D10--
- Raw text -